raiker / tarsierLinks
☆35Updated 2 years ago
Alternatives and similar repositories for tarsier
Users that are interested in tarsier are comparing it to the libraries listed below
Sorting:
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- AMD University Program HLS tutorial☆119Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- ☆71Updated 6 years ago
- ☆19Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆107Updated 5 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- ☆37Updated 6 years ago
- ☆10Updated 5 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- AXI总线连接器☆105Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆155Updated 8 months ago
- FFT implement by verilog_测试验证已通过☆58Updated 9 years ago
- ☆65Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆25Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆234Updated 2 years ago