Alternatives and similar repositories for tarsier

Users that are interested in tarsier are comparing it to the libraries listed below

• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆27Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆50Updated 6 years ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆48Updated 4 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆157Updated 2 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆33Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆29Updated 2 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆28Updated 6 years ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆81Updated 7 years ago
• mfkiwl / E203_dma
  ☆11Updated 5 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆196Updated 8 years ago
• dldldlfma / super_small_toy_tpu
  ☆46Updated 5 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆44Updated 5 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆21Updated 4 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆168Updated 6 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆241Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆114Updated 5 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆68Updated 3 years ago
• HanPU-Code / CNN_YOLO_AI_accelerator
  This project is to design yolo AI accelerator in verilog HDL.
  ☆31Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆154Updated 8 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆39Updated 8 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆41Updated 3 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 8 years ago
• GJigar / ZYNQ_CNN
  ☆19Updated 3 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆90Updated 5 years ago