☆37Jun 19, 2023Updated 3 years ago
Alternatives and similar repositories for tarsier
Users that are interested in tarsier are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- ☆13Jul 2, 2016Updated 10 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 3 years ago
- Verilog implementation of Bubble Sorter and Odd Even Transposition Sorter.☆15Nov 22, 2015Updated 10 years ago
- ☆12Oct 18, 2024Updated 2 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 6 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- This is my MTech Thesis Dissertation Topic.☆11Oct 21, 2022Updated 4 years ago
- ☆15Jul 28, 2022Updated 4 years ago
- Implementation of a circular queue in hardware using verilog.☆18Mar 22, 2019Updated 7 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆19Dec 23, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 9 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆12Sep 30, 2020Updated 6 years ago
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- Implement a bitonic sorting network on FPGA☆50Nov 6, 2021Updated 5 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆42Oct 4, 2024Updated 2 years ago
- ☆13Oct 11, 2023Updated 3 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- ☆71Aug 14, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generic FIFO implementation with optional FWFT☆65May 27, 2020Updated 6 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 8 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- Cyclostationary analysis☆10Sep 9, 2026Updated last month
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆11May 13, 2014Updated 12 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FFT generator using Chisel☆63Sep 26, 2021Updated 5 years ago
- A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.☆13Jun 17, 2022Updated 4 years ago
- A dataflow compiler☆41Oct 24, 2026Updated 2 weeks ago
- ☆15Jul 25, 2017Updated 9 years ago
- ☆17Apr 27, 2026Updated 6 months ago
- HIR high-level synthesis compiler☆11Mar 25, 2024Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆19Sep 21, 2025Updated last year