This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings
☆42Jun 3, 2020Updated 5 years ago
Alternatives and similar repositories for icc2_workshop_collaterals
Users that are interested in icc2_workshop_collaterals are comparing it to the libraries listed below
Sorting:
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago
- A 10bit SAR ADC in Sky130☆33Dec 4, 2022Updated 3 years ago
- Skywater 130nm Klayout Device Generators PDK☆30Jul 12, 2024Updated last year
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- Hdl21 Schematics☆16Jan 24, 2024Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆207Mar 8, 2020Updated 5 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated last year
- ☆17Sep 19, 2022Updated 3 years ago
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- Championship Value Prediction (CVP) simulator.☆17Feb 17, 2021Updated 5 years ago
- converts ValueChangeDump-Files (vcd) to tikz-timing-diagrams☆16Nov 19, 2021Updated 4 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆58Jun 25, 2024Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Jan 20, 2021Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆53Jun 29, 2020Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆26Feb 11, 2024Updated 2 years ago
- A VHDL code generator for wallace tree multiplier☆10Apr 15, 2020Updated 5 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆30Mar 9, 2021Updated 4 years ago
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Jun 29, 2024Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Jun 2, 2021Updated 4 years ago
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27May 1, 2018Updated 7 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆41Jun 13, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Aug 15, 2025Updated 6 months ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆36Jun 7, 2022Updated 3 years ago
- RISC-V 32-bit Linux From Scratch☆36May 10, 2020Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated this week
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- ☆38Jul 11, 2022Updated 3 years ago
- Docker 镜像下载机器 人☆13Dec 28, 2025Updated 2 months ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 3 years ago
- A static site generator for photoessays.☆10Aug 10, 2017Updated 8 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- DDRFW-UTIL tool repository☆14Feb 11, 2026Updated 3 weeks ago
- ☆21Updated this week