kunalg123 / icc2_workshop_collateralsLinks
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings
☆38Updated 5 years ago
Alternatives and similar repositories for icc2_workshop_collaterals
Users that are interested in icc2_workshop_collaterals are comparing it to the libraries listed below
Sorting:
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆196Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- This is a tutorial on standard digital design flow☆81Updated 4 years ago
- ☆219Updated 9 months ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆54Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆98Updated last year
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆32Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆28Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- ☆183Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆82Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 2 weeks ago
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year
- Some useful documents of Synopsys☆93Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆198Updated 3 months ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- ☆46Updated last year
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆13Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 3 weeks ago