This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings
☆43Jun 3, 2020Updated 6 years ago
Alternatives and similar repositories for icc2_workshop_collaterals
Users that are interested in icc2_workshop_collaterals are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repo is for synopsys icc2 flow for skywater 130nm PDK☆15Feb 7, 2023Updated 3 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Jul 12, 2024Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11May 29, 2021Updated 5 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆246Mar 8, 2020Updated 6 years ago
- Hdl21 Schematics☆17Jan 24, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago
- An implementation of 5-stages RISC-V CPU☆12Jul 22, 2022Updated 4 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 4 years ago
- APB VIP (UVM)☆18Sep 6, 2018Updated 8 years ago
- Championship Value Prediction (CVP) simulator.☆17Feb 17, 2021Updated 5 years ago
- RISC-V 32-bit Linux From Scratch☆38May 10, 2020Updated 6 years ago
- A 10bit SAR ADC in Sky130☆41Dec 4, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- AMC: Asynchronous Memory Compiler☆56Jun 29, 2020Updated 6 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆42Aug 15, 2025Updated last year
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- SAR ADC on tiny tapeout☆54Jan 29, 2025Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- A static site generator for photoessays.☆10Aug 10, 2017Updated 9 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Multi-instance MCTP daemon application.☆10Oct 7, 2024Updated last year
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆17Sep 19, 2022Updated 4 years ago
- ☆20Sep 16, 2022Updated 4 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 5 years ago
- Getting started running RISC-V Linux☆18Apr 15, 2021Updated 5 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- ☆14Oct 24, 2022Updated 3 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆29Jun 29, 2024Updated 2 years ago
- 5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.☆24Dec 4, 2022Updated 3 years ago
- 《UVM实战》书本源代码和UVM 1.1d源码及Doc☆47Mar 7, 2021Updated 5 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆39Jun 7, 2022Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆25Jan 20, 2021Updated 5 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆16Jul 31, 2024Updated 2 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago