marlls1989 / ascend-freepdk45
A free standard cell library for SDDS-NCL circuits
☆27Updated 2 years ago
Alternatives and similar repositories for ascend-freepdk45
Users that are interested in ascend-freepdk45 are comparing it to the libraries listed below
Sorting:
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- This is a tutorial on standard digital design flow☆77Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆43Updated 10 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆68Updated 4 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 4 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- ☆43Updated last year
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- SRAM☆22Updated 4 years ago
- ☆42Updated 8 months ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆24Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆62Updated 8 years ago
- ☆160Updated 2 months ago
- A RRAM addon for the NCSU FreePDK 45nm☆23Updated 3 years ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- ☆41Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- Introductory course into static timing analysis (STA).☆94Updated 3 weeks ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆25Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 6 months ago
- Mirror of Synopsys's Liberty parser library☆21Updated 6 years ago
- DATC RDF☆50Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆173Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆69Updated 4 years ago