Alternatives and similar repositories for nucleusrv:

Users that are interested in nucleusrv are comparing it to the libraries listed below

• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆69Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆140Updated 3 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆58Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆89Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• ucb-bar / testchipip
  ☆82Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆40Updated this week
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆84Updated 5 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆142Updated this week
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆100Updated 8 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 9 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆67Updated 10 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆42Updated 3 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 3 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆106Updated 4 months ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆220Updated 2 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago