merledu / nucleusrvLinks
NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
☆73Updated last week
Alternatives and similar repositories for nucleusrv
Users that are interested in nucleusrv are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 9 months ago
- 64-bit multicore Linux-capable RISC-V processor☆96Updated 3 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated last week
- Simple runtime for Pulp platforms☆48Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 9 months ago
- Naive Educational RISC V processor☆87Updated last month
- The multi-core cluster of a PULP system.☆106Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated last month
- ☆107Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- ☆148Updated last year
- The specification for the FIRRTL language☆63Updated last week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆172Updated this week
- RISC-V System on Chip Template☆159Updated last week
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated this week
- ☆85Updated 2 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- Open-source high-performance non-blocking cache☆87Updated 2 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated last week