merledu / Riscv-Single-Cycle-CoresLinks
This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala
☆10Updated 3 years ago
Alternatives and similar repositories for Riscv-Single-Cycle-Cores
Users that are interested in Riscv-Single-Cycle-Cores are comparing it to the libraries listed below
Sorting:
- A Scala library for Context-Dependent Environments☆50Updated last year
- ☆87Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Updated last year
- Provides various testers for chisel users☆100Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆243Updated last year
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- ☆30Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated 2 months ago
- A Verilog based 5-stage fully functional pipelined RISC-V Processor code.☆58Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆255Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆154Updated last year
- Chisel/Firrtl execution engine☆155Updated last year
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- This repository contains the design files of RISC-V Pipeline Core☆63Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- Chisel examples and code snippets☆265Updated 3 years ago
- ☆18Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆194Updated 4 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Verilog Configurable Cache☆192Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- Implementation of a 32-bit single core risc-v platfrom for Xilinx zcu102 board☆12Updated 6 years ago
- This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…☆15Updated 4 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆107Updated 2 months ago
- CORE-V Family of RISC-V Cores☆320Updated 11 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Updated last month
- A basic SpinalHDL project☆89Updated 5 months ago