Alternatives and similar repositories for Riscv-Single-Cycle-Cores

Users that are interested in Riscv-Single-Cycle-Cores are comparing it to the libraries listed below

• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• ucb-bar / testchipip
  ☆85Updated 2 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated 11 months ago
• merledu / Scala-Chisel-Learning-Journey
  This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…
  ☆13Updated 2 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆238Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 4 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 11 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆125Updated last week
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆121Updated 2 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆45Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆50Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated 3 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆257Updated 3 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆125Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆187Updated 2 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆73Updated this week
• nicolavianello95 / RISC-V
  Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…
  ☆16Updated 5 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 5 months ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 2 months ago
• bol-edu / caravel-soc
  ☆29Updated 2 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆141Updated 5 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 8 months ago
• vproc / vicuna
  RISC-V Zve32x Vector Coprocessor
  ☆187Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 9 months ago