merledu / Riscv-Single-Cycle-Cores
This repository contains the implementation of RISC-V Single Cycle Cores done by Undergraduate Students by using CHISEL and Functional Programming w/ Scala
☆10Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for Riscv-Single-Cycle-Cores
- This repository is for students to go through the Learning Journey for CHISEL and Funcitonal Programming with SCALA also perform tasks re…☆12Updated 2 years ago
- ☆80Updated 3 weeks ago
- A Scala library for Context-Dependent Environments☆46Updated 6 months ago
- ☆12Updated last week
- Provides various testers for chisel users☆99Updated last year
- Generic Register Interface (contains various adapters)☆99Updated last month
- ☆74Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆225Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆130Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆222Updated 2 months ago
- Verilog Configurable Cache☆167Updated 2 months ago
- Chisel/Firrtl execution engine☆153Updated 2 months ago
- Simple single-port AXI memory interface☆36Updated 5 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆97Updated 5 months ago
- Project ideas list for Google Summer of Code.☆11Updated 9 months ago
- Common RTL blocks used in SiFive's projects☆179Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆44Updated 3 months ago
- An Open-Source Design and Verification Environment for RISC-V☆75Updated 3 years ago
- ☆73Updated last year
- ☆32Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆177Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆26Updated last year
- The multi-core cluster of a PULP system.☆56Updated last week
- ☆131Updated 2 years ago
- Vector Acceleration IP core for RISC-V*☆148Updated this week
- M-extension for RISC-V cores.☆22Updated 3 years ago
- Chisel Learning Journey☆106Updated last year