zeeshanrafique23 / mduLinks
M-extension for RISC-V cores.
☆31Updated 10 months ago
Alternatives and similar repositories for mdu
Users that are interested in mdu are comparing it to the libraries listed below
Sorting:
- RISC-V Nox core☆68Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- ☆32Updated 9 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆113Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆58Updated 2 weeks ago
- Platform Level Interrupt Controller☆43Updated last year
- ☆108Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆96Updated last week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- ☆38Updated 3 years ago
- Demo SoC for SiliconCompiler.☆61Updated this week
- ☆13Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago