M-extension for RISC-V cores.
☆33Nov 21, 2024Updated last year
Alternatives and similar repositories for mdu
Users that are interested in mdu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RV32I single cycle simulation on open-source software Logisim.☆21Oct 8, 2022Updated 3 years ago
- ☆18Oct 6, 2025Updated 5 months ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- Aurora Risc-V pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps take…☆10Mar 15, 2023Updated 3 years ago
- GitHub-Shoutout is a web application that lets you win a chance to shout out by registering your username.☆10Nov 7, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Hello, GitHub fellows, thankyou for taking your time out to view my profile. Make sure to Star it :)☆14Jul 8, 2025Updated 8 months ago
- ☆38Jul 11, 2022Updated 3 years ago
- A small and simple rv32i core written in Verilog☆17Jul 29, 2022Updated 3 years ago
- BestRAG: A library for hybrid RAG, combining dense, sparse, and late interaction methods for efficient document storage and search.☆19Dec 31, 2024Updated last year
- Programing-gifs is a web app that displays different gifs related to programming at random whenever page refreshed.☆13Jan 31, 2025Updated last year
- A web application which suggests user non-clickbait video on YouTube s. Easy to use.☆12May 11, 2023Updated 2 years ago
- MediSync: Seamlessly manage hospital operations with Django, Docker, HTML, CSS, and JavaScript - a holistic healthcare solution. 🏥💻🔌☆16Apr 16, 2024Updated last year
- VGA-compatible text mode functionality☆17May 16, 2020Updated 5 years ago
- NucleusRV (rv32-imafc) - A 32-bit 5 staged pipelined risc-v core.☆78Feb 25, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- This is an Unofficial Chat-GPT Api built with Flask & playwright. Use This To test Your ChatGPT projects for free.☆19Sep 27, 2023Updated 2 years ago
- An OCaml extension for RISC-V☆16Nov 6, 2020Updated 5 years ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Dec 7, 2025Updated 3 months ago
- Controller module for RISC-V core CI/CD☆17May 23, 2025Updated 10 months ago
- Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neem…☆12Aug 26, 2022Updated 3 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated 11 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆27Jan 6, 2023Updated 3 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆13May 30, 2025Updated 10 months ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Dec 4, 2020Updated 5 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 10 months ago
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆17Oct 29, 2024Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Sep 8, 2020Updated 5 years ago
- LLM Agent for Hardware Description Language☆21Jun 7, 2025Updated 9 months ago
- A pipelined brainfuck softcore in Verilog☆19Aug 5, 2014Updated 11 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- ☆13May 8, 2025Updated 10 months ago
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆29Jul 23, 2024Updated last year
- Belief propagation on Tanner graphs (LDPC decoder)☆22Nov 20, 2021Updated 4 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- babel plugin which use jsdoc to implement strong typing in javascript☆11May 3, 2016Updated 9 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆28Oct 31, 2021Updated 4 years ago