zeeshanrafique23 / mduLinks
M-extension for RISC-V cores.
☆31Updated 11 months ago
Alternatives and similar repositories for mdu
Users that are interested in mdu are comparing it to the libraries listed below
Sorting:
- RISC-V Nox core☆68Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆98Updated last week
- ☆109Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- Platform Level Interrupt Controller☆43Updated last year
- For contributions of Chisel IP to the chisel community.☆67Updated 11 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆116Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆38Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 5 months ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 11 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- ☆33Updated 9 months ago
- The multi-core cluster of a PULP system.☆109Updated this week
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆32Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated last year