Alternatives and similar repositories for mdu

Users that are interested in mdu are comparing it to the libraries listed below

• aignacio / nox
  RISC-V Nox core
  ☆65Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• efabless / sky130_sram_macros_old
  ☆37Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆69Updated last year
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆57Updated 6 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆47Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆49Updated 8 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated this week
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated last month
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• bsc-loca / sargantana
  ☆105Updated 2 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆29Updated 4 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 7 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆102Updated last month
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆89Updated 6 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 4 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago