miscellaneousbits / linux-socfpga-sha3-miner
DE10 NANO SHA3-256 Proof of Work Miner
☆13Updated 4 years ago
Alternatives and similar repositories for linux-socfpga-sha3-miner
Users that are interested in linux-socfpga-sha3-miner are comparing it to the libraries listed below
Sorting:
- SQRL FK33 board files, example designs and scripts.☆17Updated 2 years ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- An Open Source FPGA GroestlCoin Miner☆10Updated 7 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆37Updated last year
- SHA256 in (System-) Verilog / Open Source FPGA Miner☆78Updated 7 years ago
- Bitcoin miner for Xilinx FPGAs☆97Updated 11 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 5 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Releases for the NextJTAG tool☆23Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆38Updated last month
- Docker Development Environment for SpinalHDL☆20Updated 9 months ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆27Updated 6 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆40Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- My notes for DDR3 SDRAM controller☆33Updated 2 years ago
- ☆44Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Vivado board files for the Kintex 7 HPC V2 FPGA board.☆26Updated 4 years ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- ☆17Updated 2 years ago
- ☆14Updated last month
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆78Updated last year
- ☆18Updated 3 years ago
- ☆59Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆41Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- ☆27Updated 8 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year