LSC-Unicamp / processor_ciLinks
Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.
☆17Updated 2 months ago
Alternatives and similar repositories for processor_ci
Users that are interested in processor_ci are comparing it to the libraries listed below
Sorting:
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆17Updated last year
- M-extension for RISC-V cores.☆32Updated last year
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- Simple runtime for Pulp platforms☆50Updated this week
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆76Updated 3 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- ☆29Updated 11 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- Tenstorrent Topology (TT-Topology) is a command line utility used to flash multiple NB cards on a system to use specific eth routing conf…☆16Updated last week
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- ☆17Updated last year
- RISC-V Nox core☆71Updated 6 months ago
- Wavious Wlink☆12Updated 4 years ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆55Updated this week
- The multi-core cluster of a PULP system.☆111Updated this week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆111Updated 4 months ago
- ☆26Updated 8 years ago
- A simple 5-stage Pipeline RISC-V core☆19Updated 4 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago
- ☆33Updated 3 years ago
- fpga verilog risc-v rv32i cpu☆14Updated 2 years ago
- RISC-V Nexus Trace TG documentation and reference code☆57Updated this week
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- ☆73Updated 3 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- ☆41Updated last year
- 9444 RISC-V 64IMA CPU and related tools and peripherals.☆27Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆61Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago