hossein1387 / pito_riscvLinks
A Barrel design of RV32I
☆22Updated 2 years ago
Alternatives and similar repositories for pito_riscv
Users that are interested in pito_riscv are comparing it to the libraries listed below
Sorting:
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated last year
- APB UVC ported to Verilator☆11Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- ☆40Updated 2 years ago
- RISC-V Nox core☆71Updated 6 months ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Updated 10 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- Platform Level Interrupt Controller☆43Updated last year
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Engineering Program on RTL Design for FPGA Accelerator☆33Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆32Updated last year
- A Verilog implementation of a processor cache.☆34Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- ☆60Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆79Updated 2 months ago
- 16 bit serial multiplier in SystemVerilog☆13Updated 7 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- ☆125Updated 5 months ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- ☆113Updated 2 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- SpinalHDL Hardware Math Library☆94Updated last year
- This is the base repo for our graduation project in AlexU 21☆28Updated 4 years ago