A Barrel design of RV32I
☆22Jul 30, 2023Updated 3 years ago
Alternatives and similar repositories for pito_riscv
Users that are interested in pito_riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆99Jan 5, 2025Updated last year
- Reconfigurable Binary Engine☆18Mar 23, 2021Updated 5 years ago
- Verilog Ethernet components for FPGA implementation☆26Jun 26, 2023Updated 3 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- Official implementation of "Multi-scale Feature Learning Dynamics: Insights for Double Descent".☆17Jun 10, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆32Aug 9, 2026Updated 3 weeks ago
- Code for `LLM2VEC-GEN: Generative Embeddings from Large Language Models`☆77Apr 5, 2026Updated 5 months ago
- A hands-on & simple tutorial for out-of-distribution generalization.☆18Apr 23, 2022Updated 4 years ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- ☆14May 14, 2024Updated 2 years ago
- Discovering environments with XRM☆18Dec 6, 2024Updated last year
- ☆12Nov 28, 2024Updated last year
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆20Jul 25, 2023Updated 3 years ago
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- Whisk: 16-bit serial processor for TT02☆13Sep 30, 2024Updated last year
- Quite OK image compression Verilog implementation☆24Nov 27, 2024Updated last year
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- RISCV implementation in Verilog (RV32I spec)☆17Nov 5, 2025Updated 10 months ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Vivado board files for the Kintex 7 HPC V2 FPGA board.☆26Jul 31, 2020Updated 6 years ago
- ☆12Mar 27, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Very basic real time operating system for embedded systems...☆18Sep 19, 2020Updated 5 years ago
- A VHDL code generator for wallace tree multiplier☆10Apr 15, 2020Updated 6 years ago
- ☆15May 17, 2025Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 9 years ago
- LLM4DV☆23Sep 30, 2024Updated last year
- verilog modules☆16May 4, 2020Updated 6 years ago
- ☆45Mar 12, 2025Updated last year
- 北京邮电大学 2023-2024 春季学期《数字逻辑与数字系统课程设计》——电子钟、药片装瓶系统和贪吃蛇☆25Aug 31, 2024Updated 2 years ago
- Verilog implementation of 74181 ALU chip☆13Oct 8, 2017Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FreeRTOS kernel, distributed as standard C source files with configuration header file.☆22Aug 31, 2026Updated last week
- Open source firmware for iCELink on iCESugar nano FPGA dev board.☆16Jul 3, 2022Updated 4 years ago
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆78Jan 1, 2026Updated 8 months ago
- Simple template-based UVM code generator☆31Apr 15, 2026Updated 4 months ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Apr 16, 2026Updated 4 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- CHIP-8 Emulator in Rust☆13May 11, 2018Updated 8 years ago