hossein1387 / pito_riscvLinks
A Barrel design of RV32I
☆22Updated 2 years ago
Alternatives and similar repositories for pito_riscv
Users that are interested in pito_riscv are comparing it to the libraries listed below
Sorting:
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- APB UVC ported to Verilator☆11Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- RISC-V Nox core☆68Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆31Updated 5 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆120Updated this week
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆40Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated this week
- Open source RTL simulation acceleration on commodity hardware☆30Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆16Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆29Updated last year
- ☆32Updated 2 years ago
- ☆47Updated 2 years ago
- ☆26Updated 5 years ago
- The OpenPiton Platform☆16Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- ☆60Updated 4 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 7 months ago