A Barrel design of RV32I
☆22Jul 30, 2023Updated 2 years ago
Alternatives and similar repositories for pito_riscv
Users that are interested in pito_riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆93Jan 5, 2025Updated last year
- Understanding the interplay between memorization and generalization in neural networks, featuring MAT, a learning algorithm to enhance ro…☆40Dec 19, 2024Updated last year
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 5 years ago
- Verilog Ethernet components for FPGA implementation☆23Jun 26, 2023Updated 2 years ago
- Official implementation of "Multi-scale Feature Learning Dynamics: Insights for Double Descent".☆17Jun 10, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 3 years ago
- LLM4DV☆18Sep 30, 2024Updated last year
- ☆13May 14, 2024Updated last year
- ☆12Nov 28, 2024Updated last year
- RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer…☆29Jul 12, 2024Updated last year
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- ☆13Dec 10, 2022Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 6 years ago
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISC-V Playground on Nandland Go☆16Mar 2, 2023Updated 3 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆13Jan 21, 2022Updated 4 years ago
- Verilator open-source SystemVerilog simulator and lint system☆23Mar 20, 2026Updated last week
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Vivado board files for the Kintex 7 HPC V2 FPGA board.☆25Jul 31, 2020Updated 5 years ago
- Quite OK image compression Verilog implementation☆23Nov 27, 2024Updated last year
- Very basic real time operating system for embedded systems...☆17Sep 19, 2020Updated 5 years ago
- ☆11Dec 23, 2025Updated 3 months ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Jul 14, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- CH32V003 is an ultra-cheap RISC-V MCU with 2KB SRAM, 16KB flash, and up to 18 GPIOs☆16Jan 21, 2023Updated 3 years ago
- A curated list of blockchain security Capture the Flag (CTF) competitions☆15Jan 31, 2021Updated 5 years ago
- verilog modules☆15May 4, 2020Updated 5 years ago
- FreeRTOS kernel, distributed as standard C source files with configuration header file, for use with the PSoC 6 MCU.☆22Dec 18, 2025Updated 3 months ago
- A flexible and scalable development platform for modern FPGA projects.☆42Updated this week
- ☆44Mar 12, 2025Updated last year
- Verilog implementation of 74181 ALU chip☆12Oct 8, 2017Updated 8 years ago
- A Chisel implementation for an FPGA Pin Finder thru UART☆17Sep 24, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- ☆13Mar 3, 2026Updated 3 weeks ago
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆74Jan 1, 2026Updated 2 months ago
- Download proccedings from DVCon☆23Jun 9, 2021Updated 4 years ago
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆31Oct 5, 2022Updated 3 years ago
- Simple template-based UVM code generator☆29Jan 4, 2023Updated 3 years ago
- Port face-following capabilities to the PULP-shield, and run it on the Crazyflie 2.0☆16Sep 2, 2021Updated 4 years ago
- RISC-V user-mode emulator that runs DooM☆58Apr 27, 2019Updated 6 years ago