hossein1387 / pito_riscvLinks
A Barrel design of RV32I
☆22Updated last year
Alternatives and similar repositories for pito_riscv
Users that are interested in pito_riscv are comparing it to the libraries listed below
Sorting:
- Reconfigurable Binary Engine☆17Updated 4 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆26Updated 3 weeks ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 6 months ago
- APB UVC ported to Verilator☆11Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Open source ISS and logic RISC-V 32 bit project☆54Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago
- ☆33Updated 2 years ago
- A simple DDR3 memory controller☆57Updated 2 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated last week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆71Updated 10 months ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆18Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 4 months ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- RISC-V Nox core☆65Updated 3 months ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 11 months ago
- ☆39Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated last week
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆31Updated 7 months ago
- ☆59Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- Open Source PHY v2☆29Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago