chipy-hdl / chipyLinks
chipy hdl
☆17Updated 7 years ago
Alternatives and similar repositories for chipy
Users that are interested in chipy are comparing it to the libraries listed below
Sorting:
- Example of how to use UVM with Verilator☆27Updated last month
- PicoRV☆43Updated 5 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- mantle library☆44Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 2 months ago
- Experiments with Yosys cxxrtl backend☆50Updated 10 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- Mutation Cover with Yosys (MCY)☆88Updated 3 weeks ago
- Open Processor Architecture☆26Updated 9 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- OpenFPGA☆34Updated 7 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- RISC-V processor☆32Updated 3 years ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- Visual Simulation of Register Transfer Logic☆106Updated 3 months ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- ☆87Updated last month
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- Exploration of alternative hardware description languages☆28Updated 7 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago