chipy-hdl / chipyLinks
chipy hdl
☆17Updated 7 years ago
Alternatives and similar repositories for chipy
Users that are interested in chipy are comparing it to the libraries listed below
Sorting:
- A Verilog Synthesis Regression Test☆37Updated last year
- PicoRV☆44Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 6 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- ☆23Updated 2 months ago
- System on Chip toolkit for Amaranth HDL☆92Updated 9 months ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆28Updated last week
- Open Processor Architecture☆26Updated 9 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆85Updated last week
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆65Updated last week
- Yet Another VHDL tool☆31Updated 8 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 weeks ago
- Board and connector definition files for nMigen☆30Updated 4 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Multi-threaded 32-bit embedded core family.☆24Updated 13 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- A reimplementation of a tiny stack CPU☆84Updated last year
- IRSIM switch-level simulator for digital circuits☆34Updated 3 months ago
- RISC-V processor☆31Updated 3 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- A bit-serial CPU☆19Updated 5 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago