chipy-hdl / chipyLinks
chipy hdl
☆17Updated 7 years ago
Alternatives and similar repositories for chipy
Users that are interested in chipy are comparing it to the libraries listed below
Sorting:
- ☆23Updated 5 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- PicoRV☆43Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 9 months ago
- mantle library☆44Updated 2 years ago
- Demo SoC for SiliconCompiler.☆61Updated last week
- Mutation Cover with Yosys (MCY)☆87Updated last week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Open Processor Architecture☆26Updated 9 years ago
- RISC-V processor☆32Updated 3 years ago
- System on Chip toolkit for Amaranth HDL☆93Updated last year
- Small footprint and configurable Inter-Chip communication cores☆65Updated this week
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated last month
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- Featherweight RISC-V implementation☆53Updated 3 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- OpenFPGA☆33Updated 7 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆34Updated 6 months ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- Exploration of alternative hardware description languages☆28Updated 7 years ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago