stffrdhrn / gccLinks
GCC port rewrite for OpenRISC
☆12Updated 8 months ago
Alternatives and similar repositories for gcc
Users that are interested in gcc are comparing it to the libraries listed below
Sorting:
- Mostly AVR compatible FPGA soft-core☆30Updated 4 years ago
- HDL tools layer for OpenEmbedded☆17Updated last year
- ☆54Updated 8 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21Updated 5 years ago
- PReP emulation on Power8☆32Updated 9 years ago
- MicroPython - legacy branch contain old experiments, and experimental for new work☆33Updated 4 years ago
- QSPI flash multiplexer - connect a SPI NOR flash to either an embedded system or a programmer for remote firmware tests☆54Updated 5 years ago
- Utilities for working with a Wishbone bus in an embedded device☆47Updated 5 months ago
- Chip support package for Cypress EZ-USB FX2 series microcontrollers☆84Updated last month
- simple commandline jtag stuff☆34Updated 7 years ago
- An FPGA/PCI Device Reference Platform☆32Updated 5 years ago
- A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client☆34Updated 7 years ago
- 妖刀夢渡☆63Updated 6 years ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- Project Trellis database☆14Updated 4 months ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 3 years ago
- Python app to extract a netlist of NMOS transistors from an Inkscape diagram.☆57Updated 7 years ago
- XC2064 bitstream documentation☆18Updated 7 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆58Updated 3 years ago
- Homebrew game for homebrew FPGA game console☆50Updated 5 years ago
- A small 6502 system build on a Lattice Icestick FPGA development board☆15Updated 6 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆61Updated 5 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 8 months ago
- J-core SOC for ice40 FPGA☆20Updated 6 years ago
- IBM PC Compatible SoC for a commercially available FPGA board☆73Updated 9 years ago
- The Chameleon96™ board, based on Intel® Cyclone V SoC FPGA☆15Updated 2 years ago
- A port of the OPL3 to the Panologic G1 thin client☆20Updated 6 years ago
- J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.☆28Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 6 years ago
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆49Updated 3 years ago