markcxli / FPGA_DPU
This project is to implement YOLO v3 on Xilinx FPGA with DPU
☆55Updated 5 years ago
Alternatives and similar repositories for FPGA_DPU:
Users that are interested in FPGA_DPU are comparing it to the libraries listed below
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Zynq-7000 DPU TRD☆44Updated 5 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆41Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆71Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆57Updated last year
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- The project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to d…☆15Updated 4 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 3 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆95Updated last year
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆53Updated last month
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆85Updated 6 years ago
- ☆64Updated 6 years ago
- ☆29Updated 5 months ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆72Updated last year
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 7 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago