markcxli / FPGA_DPULinks
This project is to implement YOLO v3 on Xilinx FPGA with DPU
☆63Updated 6 years ago
Alternatives and similar repositories for FPGA_DPU
Users that are interested in FPGA_DPU are comparing it to the libraries listed below
Sorting:
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- Zynq-7000 DPU TRD☆48Updated 6 years ago
- DPU on PYNQ☆242Updated 5 months ago
- ☆73Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- CNN accelerator implemented with Spinal HDL☆157Updated 2 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆170Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆105Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- A collection of tutorials for the fpgaConvNet framework.☆49Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Updated 2 years ago
- A DNN Accelerator implemented with RTL.☆69Updated last year
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆50Updated 3 weeks ago
- ☆48Updated 7 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆76Updated 7 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆164Updated 11 months ago
- Verilog implementation of Softmax function☆80Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆65Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Design for 4 x 4 Matrix Multiplication using Verilog☆35Updated 10 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Updated 4 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆114Updated 7 years ago