markcxli / FPGA_DPULinks
This project is to implement YOLO v3 on Xilinx FPGA with DPU
☆64Updated 6 years ago
Alternatives and similar repositories for FPGA_DPU
Users that are interested in FPGA_DPU are comparing it to the libraries listed below
Sorting:
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- ☆71Updated 7 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- Zynq-7000 DPU TRD☆47Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆108Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆156Updated last year
- DPU on PYNQ☆235Updated 4 months ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- 2019 SEU-Xilinx Summer School☆50Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- IC implementation of TPU☆143Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- ☆48Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆168Updated 2 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆81Updated 2 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago