markcxli / FPGA_DPU
This project is to implement YOLO v3 on Xilinx FPGA with DPU
☆41Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for FPGA_DPU
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆33Updated last year
- ☆43Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆61Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- Zynq-7000 DPU TRD☆43Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆43Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆48Updated 3 years ago
- ☆60Updated 5 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆35Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆77Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆36Updated 3 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆66Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆71Updated this week
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 5 years ago
- The second place winner for DAC-SDC 2020☆96Updated 2 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆110Updated 3 years ago
- The project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to d…☆13Updated 4 years ago
- ☆26Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆65Updated last year
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆86Updated 10 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆23Updated 3 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆24Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆22Updated 5 years ago