Master-thesis-final
☆19Oct 9, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera
Users that are interested in FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆86May 8, 2026Updated 2 weeks ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22May 18, 2026Updated last week
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆28Jul 11, 2024Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- assorted library of utility cores for amaranth HDL☆105Sep 17, 2024Updated last year
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆21Jul 22, 2024Updated last year
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆1,332Updated this week
- Tang Nano 20K top level module for Dar's Vectrex☆11Nov 14, 2023Updated 2 years ago
- tang-nano-4K mini samples☆15Feb 1, 2022Updated 4 years ago
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆17Apr 7, 2026Updated last month
- Mainline-friendly SPL for D1☆36Nov 1, 2022Updated 3 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆36Nov 29, 2024Updated last year
- FPGA implementation of the AnotherWorld CPU (equivalent to the original VM)☆16Apr 6, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simple extension boards for Olimex GateMate FPGA Board☆20Jun 30, 2025Updated 10 months ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆30Aug 16, 2021Updated 4 years ago
- Digital FM Radio Receiver for FPGA☆66Dec 26, 2015Updated 10 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Bare metal programming on the EBAZ4205 board with Zynq XC7Z010 SoC☆23Dec 10, 2024Updated last year
- 精简xboot☆18Mar 19, 2019Updated 7 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- Generate animated vector graphics for old-school 90's demos, like ST_NICCC☆18Jan 2, 2024Updated 2 years ago
- A dual-socket USB host PMOD module.☆15Mar 20, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Verilog Driver for the ILI9341 TFT Module