Juninho99 / FPGA_TangNano20k_Hand_Coded_DIP_LCD_CameraLinks
Master-thesis-final
☆19Updated last year
Alternatives and similar repositories for FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera
Users that are interested in FPGA_TangNano20k_Hand_Coded_DIP_LCD_Camera are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆26Updated 3 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- Collection of projects for various FPGA development boards☆44Updated last year
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆22Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆27Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆11Updated last week
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated this week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆27Updated 3 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆29Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- Demo projects for various Kintex FPGA boards☆59Updated 2 weeks ago
- A compact, configurable RISC-V core☆11Updated 2 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated 2 months ago
- ☆34Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 3 weeks ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- A Fully Open-Source Verilog-to-PCB Flow☆21Updated 10 months ago
- Re-coded Gowin GW1N primitives for Verilator use☆18Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago