rulai-hu / DNNDK-YOLOv3Links
"Forked" from Xilinx/Edge-AI-Platform-Tutorials
☆18Updated 5 years ago
Alternatives and similar repositories for DNNDK-YOLOv3
Users that are interested in DNNDK-YOLOv3 are comparing it to the libraries listed below
Sorting:
- Light-weighted neural network inference for object detection on small-scale FPGA board☆90Updated 6 years ago
- ☆239Updated 3 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆72Updated last year
- ☆247Updated 4 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆259Updated 2 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆72Updated 6 years ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆227Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆155Updated 5 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆111Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- ☆35Updated 5 years ago
- An Open Source Deep Learning Inference Engine Based on FPGA☆158Updated 4 years ago
- ☆53Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 5 years ago
- ☆33Updated 6 years ago
- DPU on PYNQ☆222Updated last year
- hls code zynq 7020 pynq z2 CNN☆84Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Updated 7 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- Low Precision(quantized) Yolov5☆39Updated 3 months ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆95Updated last year
- using xilinx xc6slx45 to implement mnist net☆83Updated 6 years ago
- Generator of verilog description for FPGA MobileNet implementation☆168Updated 3 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆338Updated last year
- A DNN Accelerator implemented with RTL.☆64Updated 5 months ago