Alternatives and similar repositories for DNNDK-YOLOv3:

Users that are interested in DNNDK-YOLOv3 are comparing it to the libraries listed below

• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• JunningWu / Learning-NVDLA-Notes
  NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…
  ☆225Updated 6 years ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆89Updated 6 years ago
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆71Updated 6 years ago
• wutianze / dnndk-pynqz2
  First lesson for you to use DNNDK, also it can be helpful for your AI learning
  ☆69Updated last year
• TomG008 / SkyNet
  ☆238Updated 2 years ago
• dhm2013724 / Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware
  At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA
  ☆31Updated 6 years ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆149Updated 5 years ago
• xyzxinyizhang / 2018-DAC-System-Design-Contest
  ☆53Updated 5 years ago
• Xilinx / CHaiDNN
  HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
  ☆324Updated 5 years ago
• nachiket / papaa-opencl
  OpenCL Labs for PAPAA Summer School 2016 Edition
  ☆46Updated 7 years ago
• embedeep / Free-TPU
  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…
  ☆256Updated last year
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆112Updated 4 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆111Updated 7 years ago
• Anonymous788 / YOLO_BlockCir
  ☆33Updated 6 years ago
• xjtuiair-cag / XJTU-Tripler
  XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
  ☆176Updated last year
• wutianze / pynq_car
  Start an exciting tour of building your autonomous car with Xilinx Pynq-Z2 and DPU.
  ☆14Updated 6 months ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆44Updated 4 years ago
• Xilinx / QNN-MO-PYNQ
  ☆246Updated 4 years ago
• xyzxinyizhang / 2019-DAC-System-Design-Contest
  ☆35Updated 5 years ago
• phdegen / object_detection_on_zynq_mpsoc
  ☆19Updated 7 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated 2 years ago
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆160Updated 3 years ago
• TF2-Engine / TF2
  An Open Source Deep Learning Inference Engine Based on FPGA
  ☆158Updated 4 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• cs217 / cs217.github.io
  Course Webpage for CS 217 Hardware Accelerators for Machine Learning, Stanford University
  ☆97Updated 2 years ago
• OpenDLA / OpenDLA
  A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
  ☆141Updated 7 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 3 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆33Updated 5 years ago
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆84Updated 6 years ago