sefaburakokcu / finn-quantized-yolo
Low-Precision YOLO on PYNQ with FINN
☆31Updated last year
Alternatives and similar repositories for finn-quantized-yolo:
Users that are interested in finn-quantized-yolo are comparing it to the libraries listed below
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆23Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- An FPGA Accelerator for Transformer Inference☆78Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆29Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆49Updated 2 weeks ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Open-source of MSD framework☆16Updated last year
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆43Updated 2 months ago
- A collection of tutorials for the fpgaConvNet framework.☆41Updated 6 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆106Updated last month
- ☆28Updated 4 months ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆9Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- ☆29Updated 3 years ago
- ☆14Updated last year
- ☆45Updated 6 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆37Updated 8 months ago
- C++ code for HLS FPGA implementation of transformer☆16Updated 6 months ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆38Updated 4 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago