Alternatives and similar repositories for cnn-vhdl-generator

Users that are interested in cnn-vhdl-generator are comparing it to the libraries listed below

• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆47Updated 4 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆33Updated 10 years ago
• cathalmccabe / PYNQ_tutorials
  ☆94Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆85Updated 2 months ago
• amiq-consulting / image-upscaling-CNN
  How to Accelerate an Image Upscaling CNN on FPGA Using HLS
  ☆23Updated 3 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated 2 years ago
• mvgprasanth / Systolic-Array-Matrix-Multiplication
  Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256
  ☆22Updated last year
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 7 months ago
• vipinkmenon / SpatialFilter
  ☆57Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆77Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆44Updated last year
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆58Updated 5 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 5 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆46Updated 2 years ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆52Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆66Updated 5 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 7 months ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆29Updated 4 years ago
• Xilinx / PYNQ_Bootcamp
  PYNQ Bootcamp 2019-2024 teaching materials.
  ☆48Updated 7 months ago
• ChrisZonghaoLi / cnn_conv_accelerator
  A Fix-pointed Rudimentary CNN Convolution Accelerator
  ☆15Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆41Updated 4 years ago