Alternatives and similar repositories for SNN_vhdl:

Users that are interested in SNN_vhdl are comparing it to the libraries listed below

• MinLiAmoy / rnn-fpga
  implementing a Recurrent Neural Network with binarized weight format on FPGA
  ☆22Updated 7 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆8Updated 2 years ago
• juliobg / Verilog-Multilayer-Perceptron
  HDL implementation of a pipelined multilayer perceptron (neural network)
  ☆15Updated 9 years ago
• shin-yamashita / 6th-AI-Edge-Contest
  RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.
  ☆11Updated last year
• Springbone / CC-Cam
  CC-Cam: A diffuser camera based on Pynq-Z2
  ☆18Updated 4 years ago
• eejlny / S2NN-HLS
  Spiking neural network for Zynq devices with Vivado HLS
  ☆31Updated 6 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆45Updated 4 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆100Updated 4 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆57Updated 2 years ago
• shaneleonard / neural-hardware
  Verilog library for implementing neural networks.
  ☆26Updated 10 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆45Updated 7 years ago
• AleksandarKostovic / Matrix-MAC-Unit
  Matrix Multiply and Accumulate unit written in System Verilog
  ☆10Updated 5 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆93Updated last month
• vrishbhan / Matrix-Multiplication
  Design for 4 x 4 Matrix Multiplication using Verilog
  ☆29Updated 9 years ago
• sure-trust / VLSI-Project-AXI-to-APB-Bridge
  ☆16Updated last year
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆60Updated 8 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• prateek22sri / XNOR-net-Binary-connect
  A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…
  ☆18Updated 6 years ago
• NeuroFan / Algorithmic-SAR-ADC-simulation-files
  HSPICE and MATLAB simulation files of a tracking SAR ADC
  ☆23Updated 7 months ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 4 years ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆56Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆33Updated 2 years ago
• chenhaoc / cnnhwpe
  ☆64Updated 2 years ago