isadorasophia / SNN_vhdl

Related projects ⓘ

Alternatives and complementary repositories for SNN_vhdl

• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆32Updated 3 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆19Updated 6 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆106Updated 7 years ago
• cxdzyq1110 / posture_recognition_CNN
  To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different response…
  ☆51Updated 6 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆43Updated 6 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆23Updated 5 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆98Updated 4 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• Xilinx / PYNQ-BOT
  ☆26Updated 6 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆53Updated 6 years ago
• Architech-Silica / Zynq-Zedboard-Vivado-Workshop
  Zynq Workshop for Beginners
  ☆28Updated 9 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆55Updated 2 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆39Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 6 months ago
• arpanvyas / SVM-Gaussian-Classification-FPGA
  SVM Gaussian Classifier of 30x30 greyscale image on Verilog
  ☆1Updated 4 months ago
• diaoenmao / FPGA-CNN
  FPGA implementation of Cellular Neural Network (CNN)
  ☆136Updated 6 years ago
• juliobg / Verilog-Multilayer-Perceptron
  HDL implementation of a pipelined multilayer perceptron (neural network)
  ☆14Updated 9 years ago
• suntodai / FPGA_image_processing
  Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image
  ☆59Updated 10 years ago
• FelixWinterstein / Vivado-KMeans
  Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
  ☆47Updated 7 years ago
• g0kul / vcnn
  Verilog Convolutional Neural Network on PYNQ
  ☆27Updated 6 years ago
• mtmd / FPGA_Based_CNN
  FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
  ☆173Updated 7 years ago
• liuguangxi / wifi_ldpc_codec
  Wi-Fi LDPC codec Verilog IP core
  ☆15Updated 5 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆42Updated 3 years ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆151Updated 7 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆161Updated 8 months ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆89Updated 11 months ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• zhangmozhe / microshift_compression
  Microshift Compression: An Efficient Image Compression Algorithm for Hardware
  ☆32Updated 3 years ago
• Pieter-Berteloot / PYNQ_Projects
  Pynq projects and guides
  ☆27Updated 6 years ago