[FPGA'21] CoDeNet is an efficient object detection model on PyTorch, with SOTA performance on VOC and COCO based on CenterNet and Co-Designed deformable convolution.
☆28Feb 7, 2023Updated 3 years ago
Alternatives and similar repositories for CoDeNet
Users that are interested in CoDeNet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Mar 17, 2021Updated 5 years ago
- Algorithm-hardware Co-design for Deformable Convolution☆24Jan 14, 2021Updated 5 years ago
- BitPack is a practical tool to efficiently save ultra-low precision/mixed-precision quantized models.☆58Feb 7, 2023Updated 3 years ago
- ☆15Oct 26, 2022Updated 3 years ago
- ☆43Jan 30, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Vivado HLS implementation of EDFLOW IP☆18Mar 8, 2022Updated 4 years ago
- ☆12Nov 24, 2023Updated 2 years ago
- Quantization library for PyTorch. Support low-precision and mixed-precision quantization, with hardware implementation through TVM.☆462May 15, 2023Updated 3 years ago
- Low-Precision YOLO on PYNQ with FINN☆37Nov 26, 2023Updated 2 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 7 years ago
- ☆14Feb 7, 2020Updated 6 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆11Aug 27, 2021Updated 4 years ago
- Open Source Projects from Pallas Lab☆21Oct 10, 2021Updated 4 years ago
- Code for "EigenDamage: Structured Pruning in the Kronecker-Factored Eigenbasis" https://arxiv.org/abs/1905.05934☆113Mar 3, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 2020 xilinx summer school☆20Aug 13, 2020Updated 5 years ago
- [CVPR'20] ZeroQ: A Novel Zero Shot Quantization Framework☆280Dec 8, 2023Updated 2 years ago
- An official implement of CVPR 2023 paper - NoisyQuant: Noisy Bias-Enhanced Post-Training Activation Quantization for Vision Transformers☆27Mar 13, 2024Updated 2 years ago
- BitSplit Post-trining Quantization☆49Dec 20, 2021Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆32Dec 21, 2020Updated 5 years ago
- Pytorch implementation of our paper accepted by ECCV 2022-- Fine-grained Data Distribution Alignment for Post-Training Quantization☆16Sep 13, 2022Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- ☆19Mar 21, 2023Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The CNN architecture elements implemented with RTL approach in VHDL.☆16May 9, 2019Updated 7 years ago
- DNN quantization with outlier channel splitting (ICML'19)☆114Mar 21, 2020Updated 6 years ago
- ☆19Jul 18, 2021Updated 5 years ago
- ☆11Sep 22, 2022Updated 3 years ago
- How to design a MIPI CSI interface with Efinix Trion FPGA T20F169 QUICKLY☆10Feb 6, 2020Updated 6 years ago
- UniSparse: An Intermediate Language for General Sparse Format Customization (OOPSLA'24)☆34Nov 12, 2024Updated last year
- A Convolutional Neural Network Accelerator, which increases the process of convolution calculation. Based on Xilinx HLS design suite.☆12Jul 29, 2021Updated 4 years ago
- AUTOMATIC VHDL GENERATION FOR CNN MODELS☆32Nov 16, 2022Updated 3 years ago
- All about acceleration and compression of Deep Neural Networks☆33Nov 5, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆15Apr 12, 2023Updated 3 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 10 months ago
- TLUT tool flow for parameterised configurations for FPGAs☆17Aug 5, 2024Updated last year
- Designs for finalist teams of the DAC System Design Contest☆37Jul 8, 2020Updated 6 years ago
- Angular 7/8/9 Application with PHP Back-End Example☆12Mar 4, 2020Updated 6 years ago
- Traffic-Sign-Reognition☆15Dec 18, 2020Updated 5 years ago
- a project build the SSD net in pynq-z2☆15Aug 1, 2020Updated 5 years ago