Hardware Accelerators (HwAs) constructed in Vivado HLS
☆20Jul 17, 2017Updated 8 years ago
Alternatives and similar repositories for patmos_HLS
Users that are interested in patmos_HLS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆62Aug 4, 2023Updated 2 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated last month
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- A Dataflow library for graph analytics acceleration☆14Dec 15, 2015Updated 10 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 10 years ago
- Object-Oriented Programming☆12Aug 26, 2021Updated 4 years ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- ☆29Feb 2, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 6 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆70Feb 13, 2025Updated last year
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- ☆15Mar 19, 2022Updated 4 years ago
- Virtio implementation in SystemVerilog☆49Jan 23, 2018Updated 8 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- ☆12Aug 1, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- general-cores☆21Jul 16, 2025Updated 9 months ago
- Reference HDL code for the MATRIX Creator's Spartan 6 FPGA☆28Jan 15, 2020Updated 6 years ago
- 😾CET6Cat英语六级辅导网(服务端),Django REST framework。☆10Aug 13, 2019Updated 6 years ago
- A guide on how to emulate an NVMe SPDM responder device with QEMU and Linux. Additionally, instructions on setting up and testing the (in…☆11Sep 3, 2024Updated last year
- Fine Grain FPGA Overlay Architecture and Tools☆27Nov 5, 2021Updated 4 years ago
- Open-source Verifiable Data Structures Server implementation☆13Aug 12, 2025Updated 8 months ago
- An advanced header-only exact synthesis library☆31Nov 24, 2022Updated 3 years ago
- ☆11May 30, 2018Updated 7 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Oct 18, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Mar 15, 2026Updated last month
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated 2 months ago
- A floating-point matrix multiplication implemented in hardware☆32Jan 5, 2021Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Sep 7, 2015Updated 10 years ago
- The Numato Opsis board is the first fully open source HDMI2USB board.☆13Sep 8, 2015Updated 10 years ago
- Repository containing all my presentations/tutorials/talks.☆10Sep 16, 2022Updated 3 years ago