A-T-Kristensen / patmos_HLSLinks
Hardware Accelerators (HwAs) constructed in Vivado HLS
☆20Updated 7 years ago
Alternatives and similar repositories for patmos_HLS
Users that are interested in patmos_HLS are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- FPU Generator☆20Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- ☆27Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 6 months ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- ☆44Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- ☆12Updated 5 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- SRAM☆22Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 2 weeks ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆34Updated 4 months ago
- ☆27Updated 7 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- ☆26Updated last year
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆59Updated last month
- ☆20Updated 5 years ago