Alternatives and similar repositories for patmos_HLS:

Users that are interested in patmos_HLS are comparing it to the libraries listed below

• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆20Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• gilani / fpfma
  Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)
  ☆17Updated 11 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆17Updated 7 months ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆29Updated last year
• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated last year
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆14Updated 10 years ago
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆11Updated 4 years ago
• StanfordAHA / CGRAFlow
  Integration test for entire CGRA flow
  ☆12Updated 5 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆18Updated 3 months ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆25Updated 9 months ago
• pulp-platform / axi_llc
  ☆21Updated last week
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆32Updated 3 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆11Updated this week
• cornell-brg / pymtl-tut-hls
  Tutorial for integrating PyMTL and Vivado HLS
  ☆17Updated 8 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆14Updated 10 months ago
• chipsalliance / aib-protocols
  ☆25Updated 10 months ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated last month
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆50Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆13Updated 4 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆14Updated 4 months ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• DreamCloud-Project / McSim-TLM-NoC
  Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level
  ☆10Updated 8 years ago