Alternatives and similar repositories for reloc

Users that are interested in reloc are comparing it to the libraries listed below

• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated last year
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆17Updated last year
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆35Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆45Updated 10 years ago
• Architech-Silica / Zynq-Configuration-Controller
  A configuration controller solution allowing a Zynq device to configure downstream FPGAs
  ☆14Updated 10 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆40Updated 11 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆25Updated 5 years ago
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆23Updated 4 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Updated 5 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆27Updated last year
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆19Updated 8 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated this week
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• marph91 / pico-png
  PNG encoder, implemented in VHDL
  ☆23Updated last year
• drom / spi
  spi memory controller
  ☆22Updated 9 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆19Updated 4 months ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆42Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆65Updated 2 months ago