jbornschein / soc-lm32Links
Open source/hardware SoC plattform based on the lattice mico 32 softcore
☆15Updated 15 years ago
Alternatives and similar repositories for soc-lm32
Users that are interested in soc-lm32 are comparing it to the libraries listed below
Sorting:
- DVI to LVDS Verilog converter☆24Updated 8 years ago
- Open Source ZYNQ Board☆31Updated 9 years ago
- artix-7 PCIe dev board☆29Updated 7 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Updated 9 years ago
- SD device emulator from ProjectVault☆17Updated 5 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- Xilinx Virtual Cable Daemon☆20Updated 5 years ago
- verilog core for ws2812 leds☆33Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- Misc open FPGA flow examples☆8Updated 5 years ago
- Small footprint and configurable SPI core☆42Updated last month
- Development board for Lattice Crosslink-NX 72QFN☆29Updated 4 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated last year
- mirror of https://git.elphel.com/Elphel/x393☆40Updated 2 years ago
- A CIC filter implemented in Verilog☆22Updated 9 years ago
- I want to learn [n]Migen.☆42Updated 5 years ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆18Updated 6 years ago
- ChipTools is a utility to automate FPGA build and verification☆24Updated 3 years ago
- Simple but Small Frame Grabber☆38Updated 3 years ago
- LIB:Library for interacting with an FPGA over USB☆84Updated 4 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files☆25Updated 4 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆69Updated 7 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆39Updated 2 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago