Architech-Silica / Zynq-Configuration-Controller
A configuration controller solution allowing a Zynq device to configure downstream FPGAs
☆14Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for Zynq-Configuration-Controller
- File editor for the Xilinx AXI Traffic Generator IP☆15Updated last year
- AXI DMA Check: A utility to measure DMA speeds in simulation☆12Updated 2 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆16Updated last year
- git clone of http://code.google.com/p/axi-bfm/☆17Updated 11 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆12Updated 5 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Updated 6 years ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆20Updated 8 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆15Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Extensible FPGA control platform☆54Updated last year
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆22Updated 3 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- minimal code to access ps DDR from PL☆19Updated 5 years ago
- ☆12Updated 3 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 6 years ago
- Verilog Repository for GIT☆29Updated 3 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.☆12Updated 9 years ago
- Python tools for processing Verilog files☆10Updated 12 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆13Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago