Architech-Silica / Zynq-Configuration-ControllerLinks
A configuration controller solution allowing a Zynq device to configure downstream FPGAs
☆14Updated 9 years ago
Alternatives and similar repositories for Zynq-Configuration-Controller
Users that are interested in Zynq-Configuration-Controller are comparing it to the libraries listed below
Sorting:
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Updated 7 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 6 months ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 4 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆13Updated 6 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆18Updated 7 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- minimal code to access ps DDR from PL☆20Updated 5 years ago
- Testbenches for HDL projects☆18Updated this week
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- ☆15Updated 3 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆26Updated 4 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 7 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- ☆18Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆17Updated 2 years ago
- git clone of http://code.google.com/p/axi-bfm/☆17Updated 12 years ago
- Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors☆22Updated 9 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Zynq PR Management☆13Updated 9 years ago
- ☆32Updated 2 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- A collection of Opal Kelly provided design resources☆16Updated 2 months ago