Alternatives and similar repositories for zycap

Users that are interested in zycap are comparing it to the libraries listed below

• bgottschall / reloc
  Designing Relocatable FPGA Partitions with Vivado Design Suite
  ☆10Updated 7 years ago
• Architech-Silica / Zynq-Configuration-Controller
  A configuration controller solution allowing a Zynq device to configure downstream FPGAs
  ☆13Updated 9 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 7 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 9 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• Digilent / Petalinux-Zybo-Z7-20
  ☆53Updated 2 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆22Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• laurivosandi / hdl
  Collection of hardware description languages writings and code snippets
  ☆27Updated 10 years ago
• AEW2015 / PYNQ_PR_Overlay
  Adding PR to the PYNQ Overlay
  ☆17Updated 8 years ago
• delhatch / Zynq_UDP
  Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.
  ☆26Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• marph91 / pico-png
  PNG encoder, implemented in VHDL
  ☆23Updated last year
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆39Updated 7 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆17Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• PyHDI / zynq-linux
  How to configure Debian Linux environment for Xilinx Zynq.
  ☆31Updated 8 years ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 3 years ago
• mcjtag / axis-uart
  AXI Stream UART (verilog)
  ☆11Updated 5 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated last week
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 5 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 2 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago