Alternatives and similar repositories for nscscc-wiki

Users that are interested in nscscc-wiki are comparing it to the libraries listed below

• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆134Updated 5 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆146Updated last year
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆45Updated 5 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆136Updated 2 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆299Updated 5 months ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆47Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆41Updated 5 years ago
• OSCPU / ysyx-workbench
  ☆160Updated last month
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆624Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆195Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆118Updated 5 years ago
• xiazhuo / nscc2022_personal
  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
  ☆76Updated last year
• cebarobot / Introduction-to-Computer-Architecture-Exercises
  计算机体系结构 2020秋季 UCAS 《计算机体系结构基础》第 2 版课后习题
  ☆68Updated 4 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆86Updated 6 years ago
• 14010007517 / 2020NSCSCC
  Chongqing University 2020 NSCSCC
  ☆29Updated 5 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆52Updated 4 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆33Updated 6 years ago
• lvyufeng / step_into_mips
  一步一步写MIPS CPU
  ☆855Updated 4 years ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆30Updated last year
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆182Updated 4 years ago
• CQU-CS-LABs / CO-lab-docs-CQU
  重庆大学硬件综合设计课程实验文档
  ☆44Updated 6 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• BUAA-CI-LAB / BHLA.README
  ☆17Updated last year
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆200Updated last year