SocialistDalao / UltraMIPS_NSCSCCLinks
UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
☆146Updated last year
Alternatives and similar repositories for UltraMIPS_NSCSCC
Users that are interested in UltraMIPS_NSCSCC are comparing it to the libraries listed below
Sorting:
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆41Updated 5 years ago
- NSCSCC 信息整合☆253Updated 4 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆134Updated 5 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆44Updated 5 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆62Updated last year
- 2022年龙芯杯个人赛 单发射110M(含icache)☆47Updated 3 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- ☆67Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- ☆35Updated 2 years ago
- 适用于龙芯杯团队赛入门 选手的应急cache模块☆30Updated last year
- ☆17Updated last year
- ☆160Updated last month
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 6 years ago
- ☆89Updated 2 months ago
- ☆72Updated 2 years ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 9 months ago
- ☆20Updated last year
- ☆91Updated 3 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- ☆35Updated 6 years ago
- NJU Virtual Board☆297Updated 4 months ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- ☆40Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated last month
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆31Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Asymmetric dual issue in-order microprocessor.☆33Updated 6 years ago