SocialistDalao / UltraMIPS_NSCSCC
UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
☆131Updated 10 months ago
Alternatives and similar repositories for UltraMIPS_NSCSCC:
Users that are interested in UltraMIPS_NSCSCC are comparing it to the libraries listed below
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆51Updated last year
- 2022年龙芯杯个人赛 单发射110M(含icache)☆45Updated 2 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆35Updated 4 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆124Updated 4 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- NSCSCC 信息整合☆239Updated 4 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆153Updated 6 months ago
- ☆66Updated 8 months ago
- ☆63Updated this week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- ☆85Updated 2 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated 3 weeks ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- ☆34Updated last year
- 一生一芯的信息发布和内容网站☆130Updated last year
- ☆64Updated 2 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17Updated 5 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆25Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆50Updated 2 years ago
- 2022龙芯杯个人赛三等奖作品☆14Updated last year
- ☆145Updated 7 months ago
- A RISC-V RV32I ISA Single Cycle CPU☆23Updated last year
- NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)☆64Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆77Updated 5 years ago
- 龙芯杯2021个人赛决赛最终代码☆10Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆34Updated 5 years ago
- ☆18Updated 8 months ago
- 龙芯杯21个人赛作品☆35Updated 3 years ago