Alternatives and similar repositories for UltraMIPS_NSCSCC

Users that are interested in UltraMIPS_NSCSCC are comparing it to the libraries listed below

• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 5 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆127Updated 4 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆178Updated 10 months ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆49Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆40Updated 5 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆132Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 5 years ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆83Updated last year
• OSCPU / ysyx-workbench
  ☆156Updated this week
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 4 months ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆84Updated 5 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆286Updated this week
• OSCPU / ysyxSoC
  ☆86Updated 2 weeks ago
• OSCPU / yosys-sta
  ☆78Updated 4 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 6 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆16Updated 6 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• iFuProcessor / iFuCore
  ☆20Updated last year
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆27Updated last year
• USTC-System-Courses / CECS-Lab
  ☆40Updated last year
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated 2 years ago
• BUAA-CI-LAB / BHLA.README
  ☆16Updated last year