CQU-CS-LABs / CO-lab-docs-CQU

Related projects: ⓘ

• CQU-CS-LABs / CO-lab-material-CQU
  重庆大学计算机组成原理、硬件综合设计实验材料。
  ☆12Updated last year
• 14010007517 / 2020NSCSCC
  Chongqing University 2020 NSCSCC
  ☆28Updated 3 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆31Updated 2 months ago
• TheRainstorm / CO_ext_lab-CQU
  重庆大学计组（硬综）拓展实验；
  ☆20Updated 3 years ago
• TheRainstorm / PiplineMIPS
  A 5-level pipelined MIPS CPU with branch prediction and great cache.
  ☆16Updated 3 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆41Updated 4 years ago
• y0fy / CO-lab-material-CQU
  重庆大学计算机组成原理、硬件综合设计实验材料
  ☆36Updated 3 years ago
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆11Updated last year
• cyyself / sockraw-udp
  在Linux下使用PF_PACKET的Raw Socket实现从以太网到UDP的封装，并支持IPv4 Fragment，重大18计卓班的计网Project
  ☆31Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆34Updated 4 years ago
• CQU-CS-LABs / osexp-docs-cqu
  重庆大学操作系统课程实验文档
  ☆15Updated 4 months ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆35Updated 3 years ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆32Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆21Updated 6 months ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆109Updated 3 years ago
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆97Updated 2 months ago
• nscscc2019ucas / nscscc2019ucas
  ☆32Updated 5 years ago
• FanQinFred / Cache
  重庆大学计算机学院2018级计算机体系结构cache设计
  ☆11Updated 3 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 2 months ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆44Updated 2 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆65Updated last year
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆43Updated 2 months ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆120Updated 2 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆44Updated 9 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆33Updated 2 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆34Updated last year
• cyyself / ucore-loongarch32
  将uCore移植到Loongarch 32
  ☆28Updated 10 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆25Updated 5 months ago
• fluctlight001 / Nova132
  A classic five stage pipelined processor
  ☆13Updated 6 months ago