oscourse-tsinghua / cpu-testcaseLinks
Test cases for MIPS CPU implementation
☆12Updated 6 years ago
Alternatives and similar repositories for cpu-testcase
Users that are interested in cpu-testcase are comparing it to the libraries listed below
Sorting:
- nscscc2018☆27Updated 7 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- ☆169Updated 4 years ago
- Naïve MIPS32 SoC implementation☆118Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated 3 months ago
- 5级流水线MIPS-lite微系统(北京工业大学计组课设)☆10Updated 4 years ago
- ☆21Updated 4 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆109Updated 6 years ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 6 months ago
- uCore MIPS32 porting☆18Updated 6 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Updated 5 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 6 years ago
- ☆17Updated 3 years ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆43Updated last month
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 6 years ago
- Computer System Project for Loongson FPGA Board in 2017☆54Updated 7 years ago
- ☆13Updated 5 years ago
- Hardware design with Chisel☆35Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 11 months ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆129Updated 6 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year