oscourse-tsinghua / cpu-testcaseLinks
Test cases for MIPS CPU implementation
☆12Updated 5 years ago
Alternatives and similar repositories for cpu-testcase
Users that are interested in cpu-testcase are comparing it to the libraries listed below
Sorting:
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- nscscc2018☆26Updated 6 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Documentation for Digital Design course☆20Updated last month
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated 7 months ago
- VT220-compatible console on Cyclone IV EP4CE55F23I7☆42Updated 7 years ago
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 6 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆38Updated 2 weeks ago
- Lower chisel memories to SRAM macros☆12Updated last year
- uCore MIPS32 porting☆18Updated 5 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆43Updated 11 months ago
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- ☆18Updated 3 years ago
- RV32I by cats☆16Updated last year
- Hardware design with Chisel☆33Updated 2 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 5 years ago
- ☆17Updated 3 years ago
- The 'missing header' for Chisel☆20Updated 4 months ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated 10 months ago
- Naïve MIPS32 SoC implementation☆115Updated 5 years ago
- ☆169Updated 4 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆21Updated 5 months ago
- XuanTie vendor extension Instruction Set spec☆39Updated last month
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago