oscourse-tsinghua / cpu-testcase
Test cases for MIPS CPU implementation
☆12Updated 5 years ago
Alternatives and similar repositories for cpu-testcase:
Users that are interested in cpu-testcase are comparing it to the libraries listed below
- An SoC with multiple RISC-V IMA processors.☆19Updated 6 years ago
- nscscc2018☆26Updated 6 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 5 years ago
- Documentation for Digital Design course☆19Updated last month
- Run Rocket Chip on VCU128☆30Updated 4 months ago
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 9 months ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- RV32I by cats☆17Updated last year
- The 'missing header' for Chisel☆19Updated last month
- 基于龙芯FPGA开发板的计算机综合系统实验☆25Updated 6 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 8 months ago
- VT220-compatible console on Cyclone IV EP4CE55F23I7☆40Updated 6 years ago
- ☆16Updated 3 years ago
- uCore MIPS32 porting☆18Updated 5 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- National Student Computer System Capability Challenge☆9Updated 6 years ago
- Computer System Project for Loongson FPGA Board in 2017☆52Updated 6 years ago
- ☆31Updated last month
- 计算机组成原理课程32位监控程序☆48Updated 4 years ago
- A SystemVerilog implementation of MIPS32 CPU and RIP router☆22Updated 5 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Open-Source EDA workshop for RISC-V community☆12Updated 2 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆31Updated 4 years ago
- ☆13Updated 4 years ago
- Chisel implementation of USTC RISC-V☆8Updated 4 years ago