rstar900 / Dual-Core-RISC-V-ProcessorLinks
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
☆14Updated 3 years ago
Alternatives and similar repositories for Dual-Core-RISC-V-Processor
Users that are interested in Dual-Core-RISC-V-Processor are comparing it to the libraries listed below
Sorting:
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- Advanced Architecture Labs with CVA6☆69Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- BlackParrot on Zynq☆48Updated this week
- ☆22Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆27Updated last week
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- ☆37Updated 6 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- ☆18Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 9 months ago
- ☆67Updated 4 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 7 months ago
- ☆56Updated 6 years ago
- AIA IP compliant with the RISC-V AIA spec☆45Updated 9 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 3 weeks ago
- Unit tests generator for RVV 1.0☆93Updated last month
- General Purpose AXI Direct Memory Access☆61Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆20Updated 5 months ago
- Pure digital components of a UCIe controller☆75Updated 3 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆75Updated 2 weeks ago
- Chisel Learning Journey☆110Updated 2 years ago