rstar900 / Dual-Core-RISC-V-ProcessorLinks
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
☆14Updated 3 years ago
Alternatives and similar repositories for Dual-Core-RISC-V-Processor
Users that are interested in Dual-Core-RISC-V-Processor are comparing it to the libraries listed below
Sorting:
- Advanced Architecture Labs with CVA6☆76Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 8 months ago
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- ☆22Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆58Updated 6 years ago
- "aura" my super-scalar O3 cpu core☆25Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- ☆64Updated 3 years ago
- ☆74Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated 2 years ago
- AIA IP compliant with the RISC-V AIA spec☆46Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- ☆37Updated 7 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆110Updated 4 months ago
- ☆30Updated 10 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- SystemC training aimed at TLM.☆35Updated 5 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated last year
- ☆92Updated 4 months ago
- matrix-coprocessor for RISC-V☆29Updated last month
- Example of Chisel3 Diplomacy☆11Updated 3 years ago