A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
☆14Aug 7, 2022Updated 3 years ago
Alternatives and similar repositories for Dual-Core-RISC-V-Processor
Users that are interested in Dual-Core-RISC-V-Processor are comparing it to the libraries listed below
Sorting:
- 《计算机设计与实践》测试框架☆17Jun 28, 2022Updated 3 years ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated last year
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- rewrite subset of linux 2.6 by OOP, C++ advanced topics☆10Jul 22, 2021Updated 4 years ago
- ☆15Dec 15, 2022Updated 3 years ago
- CQU Dual Issue Machine☆38Jun 23, 2024Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆18May 15, 2022Updated 3 years ago
- ☆17Mar 17, 2022Updated 3 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- Let's write an OS which can run on RISC-V in Rust from scratch!☆16Sep 18, 2023Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Dec 11, 2023Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Jan 1, 2022Updated 4 years ago
- 重庆大学计组（硬综）拓展实验；☆21Nov 25, 2020Updated 5 years ago
- Chongqing University 2020 NSCSCC☆29Oct 13, 2020Updated 5 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- nscscc2018☆27Oct 11, 2018Updated 7 years ago
- An index including some FOSS (Free and Open Source Software) about Chongqing University / 一份收录与重庆大学有关的 FOSS（自由/开源软件）的目录☆27Nov 8, 2025Updated 3 months ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Oct 31, 2024Updated last year
- ☆12Aug 12, 2022Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Jun 25, 2025Updated 8 months ago
- SLOSH-ML is a Matlab graphical user interface designed to analyze rocket propellant sloshing in space launch vehicles☆15Dec 30, 2025Updated 2 months ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Jun 3, 2022Updated 3 years ago
- Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.☆51Jul 30, 2025Updated 7 months ago
- DKMS package for various Phytium/飞腾 off-tree modules (tested with D2000/8)☆12Sep 30, 2023Updated 2 years ago
- ☆12Jul 3, 2018Updated 7 years ago
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆33Aug 27, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆49Jul 7, 2025Updated 7 months ago
- (b)ash script using curl for duodian Internet login in Chongqing University☆12Mar 27, 2022Updated 3 years ago
- A general android trace analysis framework☆12Aug 20, 2024Updated last year
- VHDL Implementation☆13Oct 9, 2014Updated 11 years ago