rstar900 / Dual-Core-RISC-V-Processor
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
☆12Updated 2 years ago
Alternatives and similar repositories for Dual-Core-RISC-V-Processor:
Users that are interested in Dual-Core-RISC-V-Processor are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆30Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 7 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆31Updated last year
- RISC-V IOMMU in verilog☆16Updated 2 years ago
- ☆23Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 weeks ago
- ☆53Updated 4 years ago
- ☆31Updated last year
- ☆21Updated 7 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆15Updated last week
- ☆41Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- An almost empty chisel project as a starting point for hardware design☆30Updated 3 weeks ago
- USB 1.1 Host and Function IP core☆20Updated 10 years ago
- ☆32Updated this week
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- ☆59Updated 3 years ago
- ☆21Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆11Updated 7 months ago
- AIA IP compliant with the RISC-V AIA spec☆35Updated 3 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆44Updated last month
- RISC-V Nox core☆62Updated 6 months ago