Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020Links
a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
☆48Updated last year
Alternatives and similar repositories for Superscalar-HIT-Core-NSCSCC2020
Users that are interested in Superscalar-HIT-Core-NSCSCC2020 are comparing it to the libraries listed below
Sorting:
- ☆34Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆80Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- ☆68Updated 4 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 7 months ago
- CQU Dual Issue Machine☆36Updated last year
- ☆36Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 2 months ago
- ☆72Updated 2 months ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated 11 months ago
- ☆22Updated 2 years ago
- ☆86Updated this week
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆137Updated last year
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- ☆66Updated 10 months ago
- ☆86Updated last month
- ☆19Updated 10 months ago
- Pick your favorite language to verify your chip.☆50Updated 2 weeks ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud☆20Updated 7 years ago
- A Study of the SiFive Inclusive L2 Cache☆64Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- ☆61Updated 2 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆25Updated 10 months ago