Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020Links
a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
☆49Updated last year
Alternatives and similar repositories for Superscalar-HIT-Core-NSCSCC2020
Users that are interested in Superscalar-HIT-Core-NSCSCC2020 are comparing it to the libraries listed below
Sorting:
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆36Updated 3 years ago
- ☆34Updated 5 years ago
- CQU Dual Issue Machine☆35Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆81Updated last year
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 8 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- ☆89Updated this week
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆42Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆138Updated last year
- Pick your favorite language to verify your chip.☆51Updated this week
- ☆35Updated last year
- ☆67Updated 5 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 3 months ago
- A Study of the SiFive Inclusive L2 Cache☆65Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- Introduction to Computer Systems (II), Spring 2021☆51Updated 4 years ago
- gem5 FS模式实验手册☆43Updated 2 years ago
- ☆73Updated 2 months ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- ☆73Updated 8 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- ☆61Updated 2 years ago
- ☆66Updated 11 months ago
- nscscc2018☆26Updated 6 years ago
- An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher☆31Updated 2 years ago
- ☆86Updated 2 months ago
- Modern co-simulation framework for RISC-V CPUs☆147Updated this week
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆22Updated 2 years ago