Silverster98 / bit_nscscc_suggestionLinks
为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助
☆130Updated 5 years ago
Alternatives and similar repositories for bit_nscscc_suggestion
Users that are interested in bit_nscscc_suggestion are comparing it to the libraries listed below
Sorting:
- NSCSCC 信息整合☆251Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆143Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆44Updated 5 years ago
- NJU Virtual Board☆291Updated last month
- 一生一芯的信息发布和内容网站☆135Updated last year
- ☆155Updated last week
- ☆35Updated 6 years ago
- 2022年龙芯杯个人赛 单发射110M(含icache)☆48Updated 3 years ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆40Updated 5 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆184Updated last year
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆61Updated last year
- Naïve MIPS32 SoC implementation☆117Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- Introduction to Computer Systems (II), Spring 2021☆52Updated 4 years ago
- Asymmetric dual issue in-order microprocessor.☆33Updated 6 years ago
- ☆35Updated 2 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆175Updated 4 years ago
- ☆67Updated last year
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆86Updated 5 years ago
- 《自己动手写CPU》一书附带的文件☆87Updated 7 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆595Updated last year
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆205Updated 3 years ago
- 龙芯杯21个人赛作品☆35Updated 4 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last month
- 重庆大学硬件综合设计课程实验文档☆39Updated 3 months ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆16Updated 6 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- MIPS CPU☆14Updated 4 years ago