trivialmips / TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
☆106Updated 6 years ago
Alternatives and similar repositories for TrivialMIPS:
Users that are interested in TrivialMIPS are comparing it to the libraries listed below
- Naïve MIPS32 SoC implementation☆114Updated 4 years ago
- Computer System Project for Loongson FPGA Board in 2017☆52Updated 6 years ago
- 计算机组成原理课程32位监控程序☆48Updated 4 years ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 10 months ago
- ☆34Updated 5 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆125Updated 4 years ago
- 计算机组成原理课程 RISC-V 监控程序,支持 32 位和 64 位☆117Updated 7 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆127Updated 5 years ago
- 中国科学院 大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session☆32Updated 7 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 3 years ago
- 基于龙芯FPGA开发板的计算机综合系统实验☆25Updated 6 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- ☆169Updated 3 years ago
- nscscc2018☆26Updated 6 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆132Updated 10 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆172Updated 3 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- Riscv32 CPU Project☆90Updated 7 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- 《自己动手写CPU》一书附带的文件☆81Updated 7 years ago
- ☆122Updated 2 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 6 months ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- 龙芯杯21个人赛作品☆35Updated 3 years ago
- 通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器☆201Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆142Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- ☆35Updated last year