trivialmips / TrivialMIPSLinks
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
☆106Updated 6 years ago
Alternatives and similar repositories for TrivialMIPS
Users that are interested in TrivialMIPS are comparing it to the libraries listed below
Sorting:
- Naïve MIPS32 SoC implementation☆115Updated 5 years ago
- 计算机组成原理课程 RISC-V 监控程序,支持 32 位和 64 位☆118Updated 10 months ago
- ☆35Updated 5 years ago
- Computer System Project for Loongson FPGA Board in 2017☆52Updated 7 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- 计算机组成原理课程32位监控程序☆50Updated 5 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆129Updated 5 years ago
- nscscc2018☆26Updated 6 years ago
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆201Updated 5 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆173Updated 4 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆126Updated 4 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- 一生一芯的信息发布和内容 网站☆131Updated last year
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆36Updated 3 years ago
- ☆169Updated 4 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- 基于龙芯FPGA开发板的计算机综合系统实验☆25Updated 6 years ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆186Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆81Updated last year
- 中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session☆32Updated 8 years ago
- This repository is used to release the experimental assignments of Computer Architecture Course from USTC☆39Updated 6 years ago
- 龙芯杯21个人赛作品☆35Updated 3 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- uCore MIPS32 porting☆18Updated 5 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆138Updated last year
- ☆287Updated last week
- NSCSCC 信息整合☆251Updated 4 years ago
- A translation project of the RISC-V reader☆175Updated last year