z4yx / NaiveMIPS-HDLView external linksLinks
Naïve MIPS32 SoC implementation
☆118Jun 23, 2020Updated 5 years ago
Alternatives and similar repositories for NaiveMIPS-HDL
Users that are interested in NaiveMIPS-HDL are comparing it to the libraries listed below
Sorting:
- Computer System Project for Loongson FPGA Board in 2017☆54Jun 3, 2018Updated 7 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆109Apr 29, 2019Updated 6 years ago
- NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.☆606Jul 7, 2020Updated 5 years ago
- 计算机组成原理课程32位监控程序☆50Jun 2, 2020Updated 5 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Jun 28, 2024Updated last year
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Dec 14, 2019Updated 6 years ago
- ☆35Sep 2, 2019Updated 6 years ago
- Dockerfile with Vivado for CI☆27Apr 17, 2020Updated 5 years ago
- NSCSCC 信息整合☆251Feb 23, 2021Updated 4 years ago
- Test cases for MIPS CPU implementation☆12Dec 26, 2019Updated 6 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 weeks ago
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 2 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- MIPS CPU☆14Dec 10, 2020Updated 5 years ago
- Rust library for low-level abstraction of MIPS processors☆31Jun 6, 2020Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆33Aug 27, 2019Updated 6 years ago
- RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core☆17Jul 20, 2023Updated 2 years ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- 基于龙芯FPGA开发板的计算机综合系统实验☆26Dec 16, 2018Updated 7 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 3 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Documentation for Router Lab☆70Nov 19, 2025Updated 2 months ago
- Lab for Network Principles since 2019-2020 fall☆175Sep 22, 2025Updated 4 months ago
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Jan 26, 2020Updated 6 years ago
- Baremetal softwares for TrivialMIPS platform☆11Aug 12, 2019Updated 6 years ago
- ucore+ repository for OS laboratory 2015☆10Jun 1, 2018Updated 7 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆147Jun 23, 2024Updated last year
- Remote JTAG server for remote debugging☆43Dec 31, 2025Updated last month
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 6 years ago
- ☆21Aug 23, 2021Updated 4 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- 网络学堂 PC 端 App☆21Feb 4, 2023Updated 3 years ago
- CQU选课状态监测☆13Aug 21, 2021Updated 4 years ago
- Yet Another AsYnc runtime for RuSt.☆33Feb 1, 2020Updated 6 years ago