z4yx / NaiveMIPS-HDLLinks
Naïve MIPS32 SoC implementation
☆115Updated 5 years ago
Alternatives and similar repositories for NaiveMIPS-HDL
Users that are interested in NaiveMIPS-HDL are comparing it to the libraries listed below
Sorting:
- ☆35Updated 5 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆107Updated 6 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- Computer System Project for Loongson FPGA Board in 2017☆53Updated 7 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- nscscc2018☆26Updated 6 years ago
- 计算机组成原理课程32位监控程序☆50Updated 5 years ago
- 一生一芯的信息发布和内容网站☆132Updated last year
- NSCSCC 信息整合☆251Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆142Updated last year
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- 为了更好地帮助后来的同学参加龙芯杯,草拟了这份建议,望对后来人有所帮助☆126Updated 4 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- This repository is used to release the experimental assignments of Computer Architecture Course from USTC☆39Updated 6 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆174Updated 4 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 9 months ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆129Updated 5 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- 龙芯杯21个人赛作品☆35Updated 3 years ago
- ☆168Updated 4 years ago
- 计算机组成原理课程 RISC-V 监控程序,支持 32 位和 64 位☆119Updated 11 months ago
- CQU Dual Issue Machine☆37Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Updated last year
- ☆35Updated 2 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- ☆122Updated 3 years ago
- Run rocket-chip on FPGA☆70Updated 9 months ago
- Wrapper for Rocket-Chip on FPGAs☆136Updated 2 years ago