Alternatives and similar repositories for ucore-thumips

Users that are interested in ucore-thumips are comparing it to the libraries listed below

• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆47Updated 5 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆46Updated 2 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆48Updated last year
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆31Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆17Updated 3 years ago
• cyyself / cpu232
  The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully
  ☆9Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆11Updated 5 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆55Updated last year
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated 11 months ago
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 2 years ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• oscourse-tsinghua / cpu-testcase
  Test cases for MIPS CPU implementation
  ☆12Updated 5 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆36Updated last year
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 8 months ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆25Updated 2 years ago