Alternatives and similar repositories for ucore-thumips

Users that are interested in ucore-thumips are comparing it to the libraries listed below

• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆108Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆118Updated 5 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆50Updated 5 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆52Updated 3 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 3 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆126Updated 2 weeks ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 10 months ago
• decaf-lang / minidecaf-tests
  The MiniDecaf test cases.
  ☆18Updated 7 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆27Updated 7 years ago
• jiegec / kb
  My knowledge base
  ☆74Updated this week
• cyyself / CDIM-SoC
  SoC for CQU Dual Issue Machine
  ☆12Updated 3 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 7 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆58Updated 2 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 6 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated last year
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆54Updated 7 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• WukLab / FPGA-OS
  ☆35Updated 4 years ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆13Updated 4 years ago