HITSZ-CDP / cdp-tests
《计算机设计与实践》测试框架
☆15Updated 2 years ago
Alternatives and similar repositories for cdp-tests:
Users that are interested in cdp-tests are comparing it to the libraries listed below
- 哈尔滨工业大学(深圳)2021年计算机系体结构实验☆13Updated 3 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 3 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆34Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆47Updated last year
- HITsz LUG 周报☆20Updated last year
- Repository of HITSZ OSA Wiki☆40Updated last month
- ☆13Updated 3 years ago
- 2022 年毕昇杯 萝杨空队 参赛项目☆13Updated last year
- 龙芯杯21个人赛作品☆35Updated 3 years ago
- 第六届龙芯杯混元形意太极门战队作品☆17Updated 2 years ago
- ☆34Updated 5 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆116Updated 6 months ago
- CQU Dual Issue Machine☆36Updated 10 months ago
- 计算机组成原理课程32位监控程序☆48Updated 4 years ago
- A fast compiler for SysY code☆18Updated 2 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.☆138Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆78Updated last year
- A summary of my projects☆49Updated last month
- An optimizing compiler in the Chinese Collegiate Student System Capability Challenge (Compiler Track) 2021☆61Updated 3 months ago
- ☆14Updated 2 years ago
- ☆35Updated last year
- A compiler for a C-like toy language (named "SysY") into ARMv7a assembly, written in C++17☆43Updated 4 years ago
- Project template for Artix-7 based Thinpad board☆46Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated last year
- Source-level operating system debugging tool that supports debugging kernel and multiple user processes synchronously. VSCode integration…☆38Updated 3 weeks ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 6 months ago
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆79Updated 10 months ago
- 2021年OS比赛获奖赛题(文档/代码开源),可用于2022年参赛同学的学习和提高☆48Updated 3 years ago
- Plagiarism detection tool in Rust (inspired by Stanford Moss)☆50Updated last month