cjhonlyone / NandFlashController
AXI Interface Nand Flash Controller (Sync mode)
☆87Updated 6 months ago
Alternatives and similar repositories for NandFlashController:
Users that are interested in NandFlashController are comparing it to the libraries listed below
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆68Updated 3 years ago
- Cortex M0 based SoC☆72Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆68Updated 8 months ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆92Updated last year
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- ☆53Updated 2 years ago
- NVMe Controller featuring Hardware Acceleration☆81Updated 3 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆143Updated 2 years ago
- ☆66Updated 3 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆78Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆113Updated 2 years ago
- Verilog SPI master and slave☆50Updated 9 years ago
- Vivado诸多IP,包括图像处理等☆191Updated 6 months ago
- Gigabit Ethernet UDP communication driver☆72Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- 视频旋转(2019FPGA大赛)☆31Updated 4 years ago
- ☆35Updated 9 years ago
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- FFT implement by verilog_测试验证已通过☆53Updated 8 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆109Updated last year
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- Verilog digital signal processing components☆126Updated 2 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆166Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆130Updated 8 months ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆140Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- ARM中通过APB总线连接的UART模块☆60Updated 5 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago