lauchinyuan / FPGA_DDR3_CtrlLinks
An AXI DDR3 SDRAM controller for FPGA
☆39Updated last year
Alternatives and similar repositories for FPGA_DDR3_Ctrl
Users that are interested in FPGA_DDR3_Ctrl are comparing it to the libraries listed below
Sorting:
- FPGA Technology Exchange Group相关文件管理☆45Updated 3 months ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆47Updated last year
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆27Updated last year
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- ☆36Updated 9 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆25Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- Open IP in Hardware Description Language.☆24Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- 这是 我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆92Updated 7 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆68Updated 4 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆25Updated last month
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- fpga跑sobel识别算法☆36Updated 4 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆35Updated 7 years ago
- ☆10Updated 5 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆19Updated last year
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆60Updated 6 years ago
- FPGA implementation of pose detection with Kalman filter. (verilog)☆35Updated 3 years ago
- ☆20Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆56Updated 3 years ago