lauchinyuan / FPGA_DDR3_CtrlLinks
An AXI DDR3 SDRAM controller for FPGA
☆36Updated last year
Alternatives and similar repositories for FPGA_DDR3_Ctrl
Users that are interested in FPGA_DDR3_Ctrl are comparing it to the libraries listed below
Sorting:
- 基于FPGA的三速以太网UDP协议栈设计☆25Updated last year
- FPGA Technology Exchange Group相关文件管理☆45Updated last month
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆47Updated last year
- verilog☆21Updated last year
- 学习AXI接口，以及xilinx DDR3 IP使用☆37Updated 8 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆18Updated last year
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- ☆10Updated 4 years ago
- fpga跑sobel识别算法☆35Updated 4 years ago
- FPGA implementation of pose detection with Kalman filter. (verilog)☆35Updated 3 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆59Updated 6 years ago
- 基于FPGA的FFT☆17Updated 6 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆66Updated 3 years ago
- 基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）☆48Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆25Updated last week
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- Cortex M0 based SoC☆73Updated 3 years ago
- 这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西☆33Updated 7 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。☆84Updated last year
- ☆36Updated 9 years ago
- FPGA实现简单的图像处理算法☆47Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆22Updated 2 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago