lauchinyuan / FPGA_DDR3_CtrlView external linksLinks
An AXI DDR3 SDRAM controller for FPGA
☆44Dec 30, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA_DDR3_Ctrl
Users that are interested in FPGA_DDR3_Ctrl are comparing it to the libraries listed below
Sorting:
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆26Oct 15, 2023Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- The system is a FPGA-based system that can recognize object in videos.☆16Apr 29, 2025Updated 9 months ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- ☆14May 15, 2023Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆85Feb 28, 2018Updated 7 years ago
- ☆32Jan 23, 2021Updated 5 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- 利用ZYNQ7020实现SAR数据采集系统，其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated 11 months ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated last year
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆16Dec 23, 2025Updated last month
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- ☆36Jun 19, 2023Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Nov 13, 2025Updated 3 months ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆51Oct 9, 2024Updated last year
- FPGA纯逻辑实现modbus通信☆22Sep 5, 2022Updated 3 years ago
- spi memory controller☆22Jan 5, 2017Updated 9 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Updated this week
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Aug 13, 2024Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆29Nov 3, 2025Updated 3 months ago
- Reservoir computing for short-and long-term prediction of chaotic systems, with tasks Lorenz and Mackey-Glass systems. Bayesian optimizat…☆29Jul 19, 2025Updated 6 months ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆209Nov 29, 2023Updated 2 years ago