libresilicon / PearlRiver

Related projects ⓘ

Alternatives and complementary repositories for PearlRiver

• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆30Updated 6 years ago
• libresilicon / process
  ☆87Updated 5 years ago
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆97Updated 6 months ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆64Updated 5 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆11Updated 7 years ago
• chipforge / PearlRiver
  1st Testwafer for LibreSilicon
  ☆15Updated 5 years ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 8 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆46Updated 7 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 6 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆45Updated 10 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• leviathanch / SITCON
  Slides for the talk I have very soon
  ☆12Updated 6 years ago
• leviathanch / libresiliconprocess
  ☆29Updated 5 years ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆73Updated 4 years ago
• betrusted-io / betrusted-soc
  Betrusted main SoC design
  ☆138Updated 11 months ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆47Updated 7 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 9 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• azonenberg / antikernel
  The Antikernel operating system project
  ☆113Updated 4 years ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆44Updated 5 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆80Updated 11 months ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆63Updated 2 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆30Updated 6 months ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆59Updated 4 years ago