Alternatives and similar repositories for PearlRiver

Users that are interested in PearlRiver are comparing it to the libraries listed below

• leviathanch / qtflow
  A Qt5 based free VLSI development tool
  ☆31Updated 7 years ago
• libresilicon / process
  ☆91Updated 6 years ago
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 6 years ago
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• riscvarchive / ISA_Formal_Spec_Public_Review
  Locus site for Public Review of Several RISC-V ISA Formal Specs
  ☆75Updated 5 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆119Updated 5 years ago
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆12Updated 8 years ago
• betrusted-io / betrusted-soc
  Betrusted main SoC design
  ☆148Updated 3 months ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 6 years ago
• leviathanch / libresiliconprocess
  ☆30Updated 6 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆25Updated 6 years ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• rubund / graywolf
  ☆113Updated 4 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 9 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated last week
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆18Updated 2 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆44Updated 3 years ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆64Updated 6 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆54Updated 4 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆111Updated 2 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 6 years ago
• ulx3s / ulx3s-toolchain
  ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts
  ☆39Updated 5 years ago
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆86Updated 3 years ago
• nitram2342 / degate
  Open source software for chip reverse engineering.
  ☆172Updated 5 years ago