Alternatives and similar repositories for FastWaveBackend

Users that are interested in FastWaveBackend are comparing it to the libraries listed below

• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆96Updated last month
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆95Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 6 months ago
• pieter3d / simview
  ☆85Updated last week
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆62Updated last year
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆47Updated last week
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆89Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated this week
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆50Updated 4 months ago
• pulp-platform / cheshire-ihp130-o
  ☆57Updated 6 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated last week
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆119Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 2 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago