Alternatives and similar repositories for FastWaveBackend

Users that are interested in FastWaveBackend are comparing it to the libraries listed below

• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆58Updated last year
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆65Updated 3 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆117Updated this week
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆30Updated last week
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆90Updated 7 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated last month
• pulp-platform / cheshire-ihp130-o
  ☆44Updated 2 months ago
• pieter3d / simview
  ☆79Updated last year
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆62Updated last week
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆151Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆50Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆45Updated 2 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 6 months ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆58Updated 6 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆48Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 8 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year