robertoBosio / NN2FPGALinks
From Pytorch model to C++ for Vitis HLS
☆20Updated this week
Alternatives and similar repositories for NN2FPGA
Users that are interested in NN2FPGA are comparing it to the libraries listed below
Sorting:
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Updated 2 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆149Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆124Updated last year
- A collection of tutorials for the fpgaConvNet framework.☆49Updated last year
- Verilog implementation of Softmax function☆80Updated 3 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Updated 4 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆55Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆77Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆46Updated 5 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago
- ☆15Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆65Updated 3 years ago
- ☆55Updated 2 years ago
- C++ code for HLS FPGA implementation of transformer☆20Updated last year
- ☆17Updated 4 years ago
- a Computing In Memory emULATOR framework☆15Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆181Updated 2 weeks ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- ☆14Updated 3 years ago