From Pytorch model to C++ for Vitis HLS
☆20Feb 24, 2026Updated last week
Alternatives and similar repositories for NN2FPGA
Users that are interested in NN2FPGA are comparing it to the libraries listed below
Sorting:
- Metrics for spiking neural networks based on torchmetrics☆13Mar 27, 2023Updated 2 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- [CVPR 2025] APHQ-ViT: Post-Training Quantization with Average Perturbation Hessian Based Reconstruction for Vision Transformers☆38Apr 7, 2025Updated 10 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Apr 7, 2019Updated 6 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆84Aug 7, 2022Updated 3 years ago
- Repository of notes, code and notebooks in Python for the book "Reinforcement Learning: An Introduction" by Richard S. Sutton and Andrew …☆37Aug 23, 2025Updated 6 months ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆39Mar 2, 2022Updated 4 years ago
- [CVPR 2025 Highlight] FIMA-Q: Post-Training Quantization for Vision Transformers by Fisher Information Matrix Approximation☆26Jun 16, 2025Updated 8 months ago
- PyTorch Quantization Framework For OCP MX Datatypes.☆16May 30, 2025Updated 9 months ago
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆13Dec 29, 2022Updated 3 years ago
- Hardware aware neural architecture search☆12Sep 29, 2025Updated 5 months ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- The official code for [ECCV2020] "HALO: Hardware-aware Learning to Optimize"☆10Mar 22, 2023Updated 2 years ago
- Format your bibtex (.bib) file to help standardize citations for conference and journal submissions☆14Nov 23, 2025Updated 3 months ago
- Codes for our paper "Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment" [NeurIPS'19 EMC2 workshop]…☆10Oct 12, 2020Updated 5 years ago
- ☆10Jun 4, 2024Updated last year
- c++ version of ViT☆12Nov 13, 2022Updated 3 years ago
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- [CVPR 2022] AlignQ: Alignment Quantization with ADMM-based Correlation Preservation☆11Jan 6, 2023Updated 3 years ago
- ☆14Jun 22, 2022Updated 3 years ago
- Simulation-based Digital Twin for Production and Logistics Material Flows☆24Feb 20, 2026Updated last week
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Signal processing features based on xtensor☆12Nov 25, 2023Updated 2 years ago
- deltaV is a bare-metal hypervisor. (Raspberry Pi-3B) [ARMv8-A]☆14May 12, 2024Updated last year
- Learn the Design of a 6-stage pipelined RISC-V CPU☆17Oct 22, 2025Updated 4 months ago
- 北航校园网网关自动登录☆10Nov 8, 2021Updated 4 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Feb 22, 2026Updated last week
- Training Quantized Neural Networks with a Full-precision Auxiliary Module☆13Jun 19, 2020Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆57Jul 9, 2021Updated 4 years ago
- ☆11Feb 24, 2025Updated last year
- Implementations of the XNOR networks☆12Aug 9, 2017Updated 8 years ago
- ☆11Apr 5, 2021Updated 4 years ago
- Awesome Quantization Paper lists with Codes☆10Feb 24, 2021Updated 5 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Deep and online learning with spiking neural networks in Python for Graphcore IPU☆10Apr 8, 2023Updated 2 years ago
- PLCT实验室2019年开放日资料(OpenDay-2019)☆11Dec 20, 2019Updated 6 years ago