The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their applications on RISC-V hardware.
☆31Apr 23, 2025Updated 11 months ago
Alternatives and similar repositories for riscv-application-profiler
Users that are interested in riscv-application-profiler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆16Oct 22, 2025Updated 5 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆16Sep 1, 2023Updated 2 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 10 months ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 5 months ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Championship Branch Prediction 2025☆68May 19, 2025Updated 11 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆97Oct 17, 2025Updated 6 months ago
- C++ header-only reasoning library☆17Jul 11, 2024Updated last year
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- ☆15Mar 28, 2026Updated 3 weeks ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆34Dec 10, 2021Updated 4 years ago
- RISC-V BSV Specification☆23Jan 18, 2020Updated 6 years ago
- Programs and Proofs -- Spring 2025 -- IITM☆20May 10, 2025Updated 11 months ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Oct 31, 2017Updated 8 years ago
- An open-source Simulation Trace Format specification☆16Nov 12, 2025Updated 5 months ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Debug waveforms with GDB☆30Nov 12, 2025Updated 5 months ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Apr 10, 2026Updated last week
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 5 years ago
- deltaV is a bare-metal hypervisor. (Raspberry Pi-3B) [ARMv8-A]☆14May 12, 2024Updated last year
- Small KVM-based hypervisor, boots Linux (WIP)☆14May 5, 2024Updated last year
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RISC-V emulator in python☆63Jul 7, 2024Updated last year
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆13Dec 29, 2022Updated 3 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- IDEA project source files☆112Updated this week
- Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm☆19Jan 4, 2026Updated 3 months ago
- A static site generator that's just Pandoc and Make☆17Apr 19, 2017Updated 9 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- An introductory guide to Bluespec (BSV)☆67May 4, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Readings in Computer Architectures☆17Dec 21, 2025Updated 3 months ago
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Sep 15, 2017Updated 8 years ago
- A simple CPU ray tracer written in Rust☆22Mar 10, 2023Updated 3 years ago
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆20Jan 20, 2023Updated 3 years ago
- C++ command shell library☆54Sep 30, 2024Updated last year