The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their applications on RISC-V hardware.
☆31Apr 23, 2025Updated last year
Alternatives and similar repositories for riscv-application-profiler
Users that are interested in riscv-application-profiler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆17Jun 30, 2026Updated 3 months ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆16Oct 22, 2025Updated 11 months ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 11 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Championship Branch Prediction 2025☆76May 19, 2025Updated last year
- C++ header-only reasoning library☆19Jul 11, 2024Updated 2 years ago
- A generic test bench written in Bluespec☆57Aug 26, 2026Updated last month
- ☆17Mar 28, 2026Updated 6 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆109Jul 3, 2026Updated 3 months ago
- Testing processors with Random Instruction Generation☆62Updated this week
- RISC-V BSV Specification☆24Apr 28, 2026Updated 5 months ago
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- An open-source Simulation Trace Format specification☆17Jun 4, 2026Updated 4 months ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆25Oct 31, 2017Updated 8 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Small KVM-based hypervisor, boots Linux (WIP)☆14May 5, 2024Updated 2 years ago
- deltaV is a bare-metal hypervisor. (Raspberry Pi-3B) [ARMv8-A]☆13May 12, 2024Updated 2 years ago
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆15Dec 29, 2022Updated 3 years ago
- ☆105Apr 16, 2026Updated 5 months ago
- RISC-V emulator in python☆64Aug 26, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- IDEA project source files☆115Apr 15, 2026Updated 5 months ago
- ☆15Dec 2, 2021Updated 4 years ago
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- ☆15Sep 27, 2022Updated 4 years ago
- RISCV full system support on gem5 related files live here☆17Jan 24, 2022Updated 4 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- An introductory guide to Bluespec (BSV)☆69May 4, 2019Updated 7 years ago
- Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm☆21Jan 4, 2026Updated 9 months ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Roofline prototype for Arm☆14Mar 25, 2024Updated 2 years ago
- Readings in Computer Architectures☆17Apr 27, 2026Updated 5 months ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆43Jun 28, 2024Updated 2 years ago
- CalBERT - Code-mixed Adaptive Language representations using BERT, published at AAAI-MAKE 2022☆12Dec 18, 2023Updated 2 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆16Jan 2, 2021Updated 5 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Sep 15, 2017Updated 9 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Jan 7, 2022Updated 4 years ago