The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their applications on RISC-V hardware.
☆31Apr 23, 2025Updated last year
Alternatives and similar repositories for riscv-application-profiler
Users that are interested in riscv-application-profiler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆16Oct 22, 2025Updated 7 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆17May 23, 2026Updated 3 weeks ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 7 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Championship Branch Prediction 2025☆71May 19, 2025Updated last year
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆102Oct 17, 2025Updated 8 months ago
- C++ header-only reasoning library☆19Jul 11, 2024Updated last year
- A generic test bench written in Bluespec☆57Dec 15, 2020Updated 5 years ago
- ☆15Mar 28, 2026Updated 2 months ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated last month
- Programs and Proofs -- Spring 2025 -- IITM☆20May 10, 2025Updated last year
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Oct 31, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open-source Simulation Trace Format specification☆17Jun 4, 2026Updated 2 weeks ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- Development area for another repo: Learn_Bluespec_and_RISCV_Design☆13Nov 10, 2025Updated 7 months ago
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 5 years ago
- Small KVM-based hypervisor, boots Linux (WIP)☆14May 5, 2024Updated 2 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 8 years ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 7 months ago
- This project presents the implementation of Quantum Key Distribution (QKD) Protocol:BB84 on FPGA. Quantum Communication Methodology has b…☆14Dec 29, 2022Updated 3 years ago
- ☆105Apr 16, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- RISC-V emulator in python☆65Jul 7, 2024Updated last year
- Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm☆19Jan 4, 2026Updated 5 months ago
- IDEA project source files☆113Apr 15, 2026Updated 2 months ago
- ☆14Sep 27, 2022Updated 3 years ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- An introductory guide to Bluespec (BSV)☆69May 4, 2019Updated 7 years ago
- Readings in Computer Architectures☆17Apr 27, 2026Updated last month
- C++ parsing library for simple formats used in logic synthesis and formal verification☆42Jun 28, 2024Updated last year
- Notes about books.☆19May 1, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Jan 7, 2022Updated 4 years ago
- A simple CPU ray tracer written in Rust☆22Mar 10, 2023Updated 3 years ago
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆19Jan 20, 2023Updated 3 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- CalBERT - Code-mixed Adaptive Language representations using BERT, published at AAAI-MAKE 2022☆13Dec 18, 2023Updated 2 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago