Knight-J / Hardware-Trojan-Detection-RTL-View external linksLinks
Used for hardware trojan detection(Based on Trust_Hub)
☆10Jul 30, 2019Updated 6 years ago
Alternatives and similar repositories for Hardware-Trojan-Detection-RTL-
Users that are interested in Hardware-Trojan-Detection-RTL- are comparing it to the libraries listed below
Sorting:
- Machine Learning Techniques for Hardware Trojan Detection☆28Sep 24, 2020Updated 5 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Feb 6, 2020Updated 6 years ago
- Environmental Studies (P/F course) - End Semester Project☆10Jun 10, 2021Updated 4 years ago
- various microcontroller stuff☆10Jun 4, 2017Updated 8 years ago
- ☆48Jul 6, 2023Updated 2 years ago
- Two-Stage ECG Signal Denoising Based Deep Convolutional Network☆13Nov 19, 2021Updated 4 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- ☆13Sep 21, 2021Updated 4 years ago
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆11Jul 9, 2020Updated 5 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 8 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- Deep learning for 12-lead ECG classification☆12Jul 6, 2023Updated 2 years ago
- GUI for SymbiYosys☆17Oct 13, 2025Updated 4 months ago
- 多媒体立体防护平台☆13May 22, 2025Updated 8 months ago
- ☆11Jul 28, 2022Updated 3 years ago
- ☆14Feb 3, 2025Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- ☆14Jul 22, 2024Updated last year
- Minimalistic RV32I RISC-V Processor in System Verilog☆19Sep 19, 2023Updated 2 years ago
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- FortifyPatch: Towards Tamper-resistant Live Patching in Linux-based Hypervisor.☆17Sep 22, 2025Updated 4 months ago
- AXI memory-mapped VGA module originally designed for the Avent Zedboard☆16Aug 2, 2016Updated 9 years ago
- Python Implementation of Pan Tompkins Algorithm for QRS peak detection☆12Dec 2, 2021Updated 4 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 10 years ago
- Anomaly detection system for heart diseases from ECG using machine learning☆12Feb 15, 2017Updated 9 years ago
- ☆11Jan 10, 2019Updated 7 years ago
- ☆14Sep 14, 2020Updated 5 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- Matlab GUI to load, plot, analyze and filter real ECG signal and model your own ECG.☆16Nov 21, 2016Updated 9 years ago
- This is a probabilistic SAT attack tool.☆13Jun 5, 2021Updated 4 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆14Jan 6, 2019Updated 7 years ago
- The interactive demo of the interpretation of the anomaly detection with Triadic Motif Fields.☆14Apr 11, 2021Updated 4 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- Rainfall prediction models (Linear and Logistic) trained on publicly available datasets from Austin, Texas☆13Jul 6, 2018Updated 7 years ago
- genetic algorithm usage for routing optimization ( pyqt )☆15Mar 24, 2019Updated 6 years ago