Alternatives and similar repositories for vhdl

Users that are interested in vhdl are comparing it to the libraries listed below

• VHDL / news
  VHDL related news.
  ☆27Updated last week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• VHDL / CoreLib
  A VHDL Core Library.
  ☆18Updated 8 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 3 weeks ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆43Updated last year
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆15Updated last month
• OSVVM / VerificationIP
  Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.
  ☆10Updated 5 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• hdl / packages
  Repo to help explain the different options users have for packaging.
  ☆19Updated 3 years ago
• drom / sta
  🕒 Static Timing Analysis diagram renderer
  ☆13Updated 2 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 5 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆22Updated 3 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆51Updated 3 years ago
• fcayci / vhdl-digital-design
  VHDL code examples for a digital design course
  ☆24Updated 6 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• PyLCARS / PythonUberHDL
  Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
  ☆36Updated 7 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• paulscherrerinstitute / PsiIpPackage
  TCL framework to package Vivado IP-Cores
  ☆14Updated 3 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆22Updated 3 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆47Updated this week
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆29Updated last year
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated 5 months ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago