一个基于AXI接口的PL端卷积加速器，可由PS端调用
☆12Apr 15, 2023Updated 3 years ago
Alternatives and similar repositories for ZYNQ_PL_CONV_ACC
Users that are interested in ZYNQ_PL_CONV_ACC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Super-resolution for mass spectrometry imaging☆19Jun 30, 2023Updated 3 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- Dual-Stage Approach Toward Hyperspectral Image Super-Resolution☆20Apr 20, 2024Updated 2 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆13Apr 29, 2025Updated last year
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- HLS Custom-Precision Floating-Point Library☆13Nov 6, 2017Updated 8 years ago
- 2024嵌赛FPGA紫光同创赛题三——PixelFuze☆13May 19, 2026Updated 2 months ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 11 months ago
- Generate an FPGA design for a TWN☆11Nov 4, 2019Updated 6 years ago
- ☆13Nov 9, 2023Updated 2 years ago
- Official implementation of "DualSR: Zero-Shot Dual Learning for Real-World Super-Resolution"☆27Sep 21, 2021Updated 4 years ago
- a riscv64 os on LicheePi4A☆16Jul 16, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- PyTorch implementation of Towards Efficient Training for Neural Network Quantization☆16Jan 16, 2020Updated 6 years ago
- [AAAI 2025] Official data and code for "TB-HSU: Hierarchical 3D Scene Understanding with Contextual Affordances"☆15Sep 11, 2025Updated 10 months ago
- ☆11Aug 2, 2024Updated last year
- ☆13Jul 2, 2016Updated 10 years ago
- Classify modulation of signals☆16Jan 16, 2020Updated 6 years ago
- 32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器与除法…☆15Aug 14, 2025Updated 11 months ago
- Unofficial Pytorch Lightning Implementation of "A New Framework for CNN-Based Speech Enhancement in the Time Domain"☆24May 9, 2023Updated 3 years ago
- Long-task-oriented video analysis skill for Claude Code (/vea) — resumable staged execution, automatic parallel scoring, OpenClaw orchest…☆24Apr 22, 2026Updated 3 months ago
- my first ever browser game☆10Jun 21, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Research about dataflow architecture☆15Nov 30, 2023Updated 2 years ago
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- Quantize pytorch model, support post-training quantization and quantization aware training methods☆15Jun 15, 2023Updated 3 years ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- 集成电路设计大赛ARM杯作品，获得2021年ARM企业杯☆17Sep 26, 2021Updated 4 years ago
- FPGA实现动态图像识别☆24Jul 31, 2020Updated 5 years ago
- ☆11Nov 22, 2025Updated 8 months ago
- Testbenches for HDL projects☆23Jul 10, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块☆19Jan 12, 2023Updated 3 years ago
- ☆55Apr 19, 2019Updated 7 years ago
- Python C++ Code Manager☆15Sep 29, 2024Updated last year
- Toolbox for Evaluation of AEC/AES Systems☆39Feb 18, 2026Updated 5 months ago
- The seL4 microkernel with loongarch support, see official repositories at https://github.com/seL4☆21Jan 30, 2023Updated 3 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆21Apr 8, 2024Updated 2 years ago
- Welcome to CV-PCL Viewer! This software has simple image and video processing functions, as well as the ability to visualize point cloud …☆16Jul 20, 2024Updated 2 years ago