Alternatives and similar repositories for Synopsys-Documents:

Users that are interested in Synopsys-Documents are comparing it to the libraries listed below

• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆145Updated this week
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆112Updated 10 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆100Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆49Updated 6 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆60Updated last year
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆169Updated 6 years ago
• ForrestBlue / cortexm0ds
  ☆62Updated 9 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆132Updated 2 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆114Updated 7 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆99Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆102Updated 4 months ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆53Updated 3 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆201Updated last year
• accellera-official / uvm-core
  ☆82Updated 8 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆84Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆140Updated 6 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆148Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆32Updated 6 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆152Updated last week
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆63Updated 8 months ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆190Updated 4 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆35Updated last year