hyf6661669 / Synopsys-DocumentsView external linksLinks
Some useful documents of Synopsys
☆96Nov 5, 2021Updated 4 years ago
Alternatives and similar repositories for Synopsys-Documents
Users that are interested in Synopsys-Documents are comparing it to the libraries listed below
Sorting:
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- ☆10Aug 30, 2024Updated last year
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆52Apr 9, 2025Updated 10 months ago
- ☆11Jul 28, 2022Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Wishbone SATA Controller☆24Oct 16, 2025Updated 3 months ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated last year
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆100Jan 27, 2024Updated 2 years ago
- Novel GUI Based UVM Testbench Template Builder☆149Apr 14, 2021Updated 4 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- Open source process design kit for 28nm open process☆72Apr 23, 2024Updated last year
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 8 months ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆18Feb 4, 2026Updated last week
- ☆20Apr 2, 2023Updated 2 years ago
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆35Aug 12, 2020Updated 5 years ago
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆64Oct 18, 2025Updated 3 months ago
- ☆14May 30, 2021Updated 4 years ago
- Awesome ASIC design verification☆341Feb 9, 2022Updated 4 years ago
- A dedicated graphical processor for ray tracing☆21Jun 7, 2021Updated 4 years ago
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated last year
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Apr 29, 2024Updated last year
- [NYCU 2021 Spring] Digital Circuits and Systems☆22Jan 26, 2024Updated 2 years ago
- Verification IP for I2C protocol☆51Sep 22, 2021Updated 4 years ago
- This is the repo for the VERDI project, written in java.☆20Dec 18, 2025Updated last month
- ☆21Dec 19, 2025Updated last month
- An RTL generator for a last-level shared inclusive TileLink cache controller☆24Jan 17, 2025Updated last year
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆22Sep 2, 2023Updated 2 years ago
- Implementation of the PCIe physical layer☆60Jul 11, 2025Updated 7 months ago
- AMBA bus lecture material☆508Jan 21, 2020Updated 6 years ago
- ☆29Feb 20, 2024Updated last year
- [WIP] Dockerize Synopsys/Cadence EDA tools☆96Mar 29, 2019Updated 6 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆238Jul 16, 2023Updated 2 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆28Mar 23, 2024Updated last year