Some useful documents of Synopsys
☆103Nov 5, 2021Updated 4 years ago
Alternatives and similar repositories for Synopsys-Documents
Users that are interested in Synopsys-Documents are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- ☆10Aug 30, 2024Updated last year
- SPI-Flash XIP Interface (Verilog)☆49Oct 24, 2021Updated 4 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- This is the repo for the VERDI project, written in java.☆20Dec 18, 2025Updated 5 months ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆27Sep 8, 2024Updated last year
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆76Oct 18, 2025Updated 7 months ago
- ☆15Jul 28, 2022Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆105Jan 27, 2024Updated 2 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Open source process design kit for 28nm open process☆79Apr 23, 2024Updated 2 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 7 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Novel GUI Based UVM Testbench Template Builder☆153Apr 14, 2021Updated 5 years ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆43Apr 5, 2025Updated last year
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated 2 years ago
- ☆22Apr 2, 2023Updated 3 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆29Apr 29, 2024Updated 2 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆509Jul 18, 2025Updated 10 months ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- SoC Based on ARM Cortex-M3☆39May 16, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules require…☆36Aug 12, 2020Updated 5 years ago
- ☆12Mar 10, 2023Updated 3 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆19Apr 11, 2026Updated last month
- [WIP] Dockerize Synopsys/Cadence EDA tools☆94Mar 29, 2019Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 10 years ago
- ☆15May 30, 2021Updated 4 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- Awesome ASIC design verification☆355Feb 9, 2022Updated 4 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- ☆16Dec 4, 2021Updated 4 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆22Sep 2, 2023Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- verilog_instance.vim: create instantiation of ports from port declaration☆31Mar 13, 2023Updated 3 years ago
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11May 1, 2026Updated 2 weeks ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 4 months ago