hyf6661669 / Synopsys-Documents
Some useful documents of Synopsys
☆41Updated 2 years ago
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- A verilog implementation for Network-on-Chip☆60Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆112Updated 3 months ago
- AXI总线连接器☆89Updated 4 years ago
- ☆19Updated 8 months ago
- AXI DMA 32 / 64 bits☆95Updated 10 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆65Updated 5 years ago
- ☆24Updated 5 years ago
- ☆51Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆32Updated 2 years ago
- AXI Interconnect☆44Updated 3 years ago
- AHB DMA 32 / 64 bits☆48Updated 10 years ago
- round robin arbiter☆66Updated 10 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆79Updated 3 years ago
- AXI4 BFM in Verilog☆32Updated 7 years ago
- 3×3脉动阵列乘法器☆33Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆28Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆82Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆51Updated last month
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆19Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆62Updated last year
- UVM实战随书源码☆42Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆66Updated 6 years ago
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆38Updated 2 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆83Updated 10 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 11 years ago
- ahb scram controller, design and verification☆25Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆47Updated last year
- AMBA bus generator including AXI, AHB, and APB☆87Updated 3 years ago