Alternatives and similar repositories for Synopsys-Documents:

Users that are interested in Synopsys-Documents are comparing it to the libraries listed below

• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆111Updated 10 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• ForrestBlue / cortexm0ds
  ☆61Updated 9 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆142Updated last week
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆72Updated 7 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆49Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆98Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆167Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆99Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆82Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆198Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆143Updated 2 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆129Updated 2 years ago
• abdelazeem201 / ICC2_scripts
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
  ☆16Updated last year
• RV-BOSC / OpenNoC
  ☆136Updated last week
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆112Updated 7 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆34Updated 11 months ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆119Updated 3 years ago
• accellera-official / uvm-core
  ☆81Updated 7 months ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆61Updated 8 months ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆16Updated 11 months ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆88Updated 11 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆184Updated 4 years ago