hyf6661669 / Synopsys-DocumentsLinks
Some useful documents of Synopsys
☆91Updated 4 years ago
Alternatives and similar repositories for Synopsys-Documents
Users that are interested in Synopsys-Documents are comparing it to the libraries listed below
Sorting:
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆228Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆183Updated 3 months ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- ☆72Updated 9 years ago
- AXI总线连接器☆105Updated 5 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆108Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆114Updated 4 years ago
- Novel GUI Based UVM Testbench Template Builder☆145Updated 4 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- UVM实战随书源码☆56Updated 6 years ago
- VIP for AXI Protocol☆158Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆187Updated 7 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆131Updated 8 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- This is the repository for the IEEE version of the book☆75Updated 5 years ago
- UVM AHB VIP☆88Updated 2 months ago
- This is the main repository for all the examples for the book Practical UVM☆210Updated 5 years ago
- ☆209Updated 5 months ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆156Updated 5 years ago
- This is for uvm_tb_gen☆47Updated 9 months ago
- Awesome ASIC design verification☆334Updated 3 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆113Updated 11 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- AHB3-Lite Interconnect☆104Updated last year
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- UVM examples and projects☆149Updated 5 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆138Updated 7 years ago