Baechu44 / ic_contestLinks
☆10Updated last year
Alternatives and similar repositories for ic_contest
Users that are interested in ic_contest are comparing it to the libraries listed below
Sorting:
- ☆14Updated 4 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆20Updated last year
- IC Contest☆41Updated 2 years ago
- ☆19Updated 2 years ago
- 紀錄一下自己寫過的所有Lab☆35Updated last year
- IC-contest 2012~2024☆20Updated last year
- 交通大學iclab 2023 fall☆42Updated 11 months ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆99Updated 5 months ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆13Updated 2 years ago
- Computer-Aided VLSI System Design☆21Updated 11 months ago
- A collection of commonly asked RTL design interview questions☆32Updated 8 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆53Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- ☆41Updated 2 years ago
- ☆10Updated last year
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆136Updated last year
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆18Updated 2 years ago
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆54Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- 交大電子所-積體電路實驗設計-李鎮宜教授☆13Updated last year
- 2D Systolic Array Multiplier☆20Updated last year
- ☆19Updated 5 months ago
- ☆13Updated 3 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆187Updated 2 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆20Updated last year
- ☆29Updated this week
- Some useful documents of Synopsys☆85Updated 3 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆44Updated 2 years ago