Baechu44 / ic_contestLinks
☆10Updated last year
Alternatives and similar repositories for ic_contest
Users that are interested in ic_contest are comparing it to the libraries listed below
Sorting:
- ☆14Updated 4 years ago
- IC Contest☆42Updated 2 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆21Updated last year
- ☆19Updated 2 years ago
- 交通大學iclab 2023 fall☆44Updated last year
- IC-contest 2012~2024☆21Updated last year
- 紀錄一下自己寫過的所有Lab☆38Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- ☆43Updated 2 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理☆111Updated 7 months ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆19Updated 2 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆54Updated 2 years ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Updated 2 years ago
- Computer-Aided VLSI System Design☆23Updated last year
- ☆11Updated last year
- A collection of commonly asked RTL design interview questions☆36Updated 8 years ago
- ☆31Updated 2 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆15Updated 5 years ago
- ☆19Updated 7 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆46Updated 3 years ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆148Updated last year
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆27Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆135Updated 7 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- Some useful documents of Synopsys☆90Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆171Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆40Updated last year