This is the repo for the VERDI project, written in java.
☆21Dec 18, 2025Updated 10 months ago
Alternatives and similar repositories for VERDI
Users that are interested in VERDI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Download YouTube videos and audio with ease (support playlists). Easy to use GUI for yt-dlp written in Qt C++.☆11Feb 6, 2025Updated last year
- Modelsim QEMU Unicorn integration via the FLI☆15Oct 19, 2025Updated last year
- ☆11Apr 18, 2026Updated 6 months ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- 树莓派自动播报温湿度到QQ空间☆19Oct 28, 2017Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Calculate Ethernet CRC32/FCS for a captured frame☆12Jun 5, 2026Updated 4 months ago
- Python script to manage Questa/Modelsim simulations☆14Jan 2, 2014Updated 12 years ago
- Verilog-HDL codes, Tcl files, and etc. for TSMC_65nm☆12Jul 2, 2019Updated 7 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- ☆13May 8, 2022Updated 4 years ago
- CNN Baseline for Image Compression☆10Nov 11, 2018Updated 7 years ago
- Language for simplifying parameterized RTL design☆13Apr 3, 2026Updated 7 months ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- UVM☆14Mar 16, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AMBA bus lecture material☆11Jan 21, 2020Updated 6 years ago
- SiCo(矽科)— 基于 Codex CLI 的定制集成电路设计平台智能助手☆26Oct 23, 2026Updated last week
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 9 years ago
- Benchmarking execution time of AlexNet CNN on FPGA and GPU. Developed AlexNet in opencl.☆11Oct 9, 2019Updated 7 years ago
- Exercises for Design of Integrated circuits☆17Dec 28, 2023Updated 2 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- For OFW 5.05/Для ПО 5.05☆11Mar 18, 2021Updated 5 years ago
- Translates the DSD/DSF file into WAV file written in C for learning,☆12Feb 21, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog RTL Linter for YoSys☆25Nov 22, 2024Updated last year
- ☆12Jul 4, 2016Updated 10 years ago
- Extension support for VS Code Embedded Debug Extension☆13Apr 16, 2026Updated 6 months ago
- Note repository for studying Peripheral Component Interconnect Express (PCIe) and Compute Express Link (CXL).☆17Feb 17, 2025Updated last year
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- APB verification using UVM☆15Sep 7, 2026Updated last month
- Design of miller compensated 2 stage opamp using open source SKY130PDK☆19Jun 18, 2025Updated last year
- 🥢像老乡鸡🐔那样做饭。文字来自《老乡鸡菜品溯源报告》,并做归纳、编辑与整理。CookLikeHOC.☆12Sep 18, 2025Updated last year
- UVM Testbench for synchronus fifo☆21Aug 28, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- HiSilicon ip camera SoCs SystemRDL registers description☆12Oct 18, 2023Updated 3 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- 该部分为自己在学习tensorflow2.0中实现的各种模型还有算法,供大家参考☆19Jul 30, 2020Updated 6 years ago
- An app that lists all Xbox Game Pass games (console only) with their Metacritic scores.☆18Apr 2, 2024Updated 2 years ago
- GameBoy Advance Zedboard Implementation☆18Dec 27, 2016Updated 9 years ago
- Synthesizable temperature sensor for Tiny Tapeout 03, developed by IIC@JKU.☆22Jan 1, 2024Updated 2 years ago