Alternatives and similar repositories for huaweicloud-fpga:

Users that are interested in huaweicloud-fpga are comparing it to the libraries listed below

• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆101Updated 2 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆33Updated 6 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 6 years ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆41Updated last year
• fpgasystems / davos
  Distributed Accelerator OS
  ☆61Updated 2 years ago
• Huawei / huaweicloud-fpga
  Obsolete repository of official HUAWEI CLOUD FPGA Development Kit //github.com/huaweicloud/huaweicloud-fpga
  ☆26Updated 6 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆43Updated last year
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 3 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆70Updated 10 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• h-nasiri / Zynq-Linux-DMA
  DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.
  ☆38Updated 8 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• antmicro / nvme-verilog-pcie
  ☆53Updated 2 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆109Updated last year
• aiminickwong / H264
  H264视频解码verilog实现
  ☆78Updated 7 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆33Updated last month
• Xilinx / pcie-model
  PCI Express controller model
  ☆48Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆57Updated 3 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆72Updated 3 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆31Updated 8 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago