Alternatives and similar repositories for make_for_vivado

Users that are interested in make_for_vivado are comparing it to the libraries listed below

• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆17Updated 10 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆35Updated 8 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 6 years ago
• open-design / riscv-soc-cores
  ☆39Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆42Updated 8 months ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆37Updated last week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated 2 weeks ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆93Updated 5 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆31Updated last month
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆36Updated last month
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆31Updated 5 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆31Updated last year
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago