Alternatives and similar repositories for make_for_vivado

Users that are interested in make_for_vivado are comparing it to the libraries listed below

• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆17Updated 9 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 6 months ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆76Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• open-design / riscv-soc-cores
  ☆38Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆30Updated 5 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 5 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆45Updated 5 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated 2 weeks ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 9 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 5 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated 2 weeks ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆27Updated 5 years ago