Alternatives and similar repositories for fpgahdl_xilinx:

Users that are interested in fpgahdl_xilinx are comparing it to the libraries listed below

• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆144Updated last month
• Avnet / hdl
  ☆111Updated 3 weeks ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆127Updated 10 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆168Updated 12 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆197Updated 11 months ago
• CospanDesign / nysa-sata
  ☆83Updated 7 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆119Updated 2 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆53Updated 9 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆122Updated 4 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆49Updated 3 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆61Updated 2 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆75Updated 5 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆30Updated 5 years ago
• freecores / i2c
  I2C controller core
  ☆39Updated 2 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆104Updated last year
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆35Updated 3 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆55Updated 2 years ago
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆279Updated last year
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆93Updated 6 years ago
• jamieiles / uart
  Verilog UART
  ☆159Updated 11 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆100Updated 6 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆49Updated 10 years ago