Alternatives and similar repositories for fpgahdl_xilinx:

Users that are interested in fpgahdl_xilinx are comparing it to the libraries listed below

• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆174Updated 12 years ago
• fpgadeveloper / zedboard-axi-dma
  Demonstration of the AXI DMA engine on the ZedBoard
  ☆53Updated 4 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated 2 months ago
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆100Updated 6 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆53Updated 3 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆81Updated 5 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• CospanDesign / nysa-sata
  ☆85Updated 8 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆106Updated last year
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆30Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆35Updated 3 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 5 months ago
• Avnet / hdl
  ☆111Updated last month
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆66Updated 7 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆22Updated 5 years ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆60Updated 10 years ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆65Updated 2 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆56Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆70Updated 6 years ago
• ATaylorCEngFIET / Hackster
  Files used with hackster examples
  ☆145Updated 4 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆75Updated 5 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆33Updated 9 years ago
• imrickysu / ZYNQ-Cookbook
  This is a wiki and code sharing for ZYNQ
  ☆71Updated 9 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆70Updated 11 months ago