pbridd / lzrw1-compression-core
This is the repository for a verilog implementation of a lzrw1 compression core
☆18Updated 7 years ago
Alternatives and similar repositories for lzrw1-compression-core:
Users that are interested in lzrw1-compression-core are comparing it to the libraries listed below
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- ☆25Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- ☆20Updated 5 years ago
- ☆38Updated last year
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- ☆15Updated 3 years ago
- ☆27Updated 3 weeks ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 5 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆13Updated 2 weeks ago
- A simple, scalable, source-synchronous, all-digital DDR link☆25Updated last week
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆44Updated 2 weeks ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆17Updated 8 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago