This is the repository for a verilog implementation of a lzrw1 compression core
☆20Dec 8, 2017Updated 8 years ago
Alternatives and similar repositories for lzrw1-compression-core
Users that are interested in lzrw1-compression-core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A command-line tool for convert SVG image to PDF file☆17Mar 29, 2025Updated last year
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 11 years ago
- am_fft.h - A single-header library for power-of-two sized 1D and 2D FFTs☆31Feb 5, 2018Updated 8 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- ☆20Aug 2, 2025Updated last year
- ☆10Jan 15, 2023Updated 3 years ago
- Display Stream Compression 1.2a☆17Oct 18, 2023Updated 2 years ago
- ☆11Jan 21, 2019Updated 7 years ago
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated 4 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- General Purpose AXI Direct Memory Access☆82May 12, 2024Updated 2 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Firmware / software / Verilog for the Photon camera☆18Oct 8, 2026Updated last week
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago
- kenDryte K210 Cloud Build Support☆11Oct 24, 2018Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆33Feb 6, 2023Updated 3 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- Tools for SystemVerilog development.☆15Jan 3, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- IR image processing and demo on a Zybo Z7-20 using a Raspberry Pi night vision vamera☆14Aug 30, 2021Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆35Jun 22, 2024Updated 2 years ago
- 6800% faster "os" module replacement. A drop-in replacement for Python's standard 'OS' module. Fully-rewritten, optimized, and speeded-up…☆18Feb 20, 2023Updated 3 years ago
- Knowledge Graph of FPGA☆14Aug 21, 2021Updated 5 years ago
- A small EEPROM tool for the FTDI chips (forked from http://developer.intra2net.com/git/?p=ftdi_eeprom)☆10Jul 1, 2015Updated 11 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- xk264：AVC/H.264 Video Encoder IP Core (RTL)☆67Mar 22, 2023Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Repository for GIT☆37May 4, 2021Updated 5 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 2 months ago
- ☆21Dec 9, 2018Updated 7 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆50Jun 19, 2024Updated 2 years ago
- ☆20Mar 18, 2022Updated 4 years ago
- Verilog wishbone components☆135Jan 5, 2024Updated 2 years ago
- ☆17Jun 5, 2024Updated 2 years ago